Imagine this year with 2nm get BS-PDN (Backside Power Delivery Network) with innovation architecture chips from Apple
TSMC N2 this year is GAA but not BS-PDN. Next year should be BSPDN.
There are two interesting elements here that may make interop between Intel and TSMC less simple than interop between Samsung and TSMC.
1. If you have a backside metal layer, why limit it just to power delivery? Why not use it for other routine clutter (most obviously clock), so that you have more flexibility and space for signal wiring? This is feasible with how TSMC is doing BS-PDN; it is much less feasible with how Intel is doing it. (This is essentially why Intel got there first; they chose an implementation that is simpler but much less flexible and forward looking.)
This fact is of some interest to Apple, who have already submitted some patents describing how, for example, they would restructure SRAM to be faster and denser if they had access to a more sophisticated wiring layer on the back side (eg 2022
https://patents.google.com/patent/US20230298996A1 Backside Routing Implementation in SRAM Arrays)
So the question is: will Intel restructure their BSPDN to give Apple the flexibility they want? And will this happen before TSMC provide BSPDN?
2. That's fairly near term (maybe two or three years out). Slightly further out is a different idea. Your basic chip consists of a layer of logic, then multiple (20 or so) layers of metal wiring above that logic. Can you use that space, those layers of metal wiring interleaved with dielectric, for anything else? This is already being done today with MIM (Metal Insulator Metal) capacitors being placed between some metal layers, but can we be more ambitious?
Apple have suggested at least three types of functionality that could be placed in such a layer
- simplest is power transistors that control the voltage delivered to some region of the chip
- next up is the buffer/inverter/amplifiers that boost a signal that is traveling long distance from one region of the chip to another
- 3rd and fanciest is SRAM (not necessarily as dense or fast as "real" SRAM, but heck, there's a lot of area available if you can get this idea to work...)
Here's one example of such a patent: (2026)
https://patents.google.com/patent/US20260090359A1 BEOL Power Switch Devices
So these all seem like good ideas. Why weren't they implemented 50 years ago? The problem is that transistor processing is hot enough to ruin metal layers, which is why we have one layer of transistors laid down, then lots of of metal layers but no more transistors.
What has changed recently is the ability to manipulate so-called 2D materials, which can provide transistor functionality, but can be manipulated at lower temperatures. Making it feasible (even if these 2D material transistors are not as performant as good old doped silicon) to lay down additional layers of transistor between metal layers.
Both Intel and TSMC claimed breakthroughs in 2D material processing in 2025. So now we see which of them is first to provide something like I've described in an actual process...
Point is, there are interesting things happening that could substantially modify how a chip is designed/fabricated, enough so that it would not be trivial (maybe not even possible) to move a chip exploiting back-side clock and signal, or top metal layer power transistors to a process that does not offer this functionality.
BTW you may have noticed a common theme in both these points – the adding functionality by multiple layers on what used to be a simple transistors followed by 20 or so metal layers. The generic "marketing" name for this CMOS 2.0 Right now the only place you'll see this name is a few publications from imec, but expect to see a lot more of it over the next decade or so. This is, in a sense, the West's equivalent to Huawei's "folded logic". It began earlier, and the first product will likely ship later, but it's vastly more ambitious and more powerful.