BareFeats get their hands on an 8 core

Discussion in 'Mac Pro' started by sdhollman, Apr 10, 2007.

  1. sdhollman macrumors regular

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    #1
  2. yellow Moderator emeritus

    yellow

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    #2
    A very interesting read. If true (the whole RAM bottleneck), there will be a lot of disappointed (irate?) early adopters.
     
  3. Diatribe macrumors 601

    Diatribe

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    #3
    Nice link, ty. Too bad the CPU is being held back by the memory.
     
  4. andiwm2003 macrumors 601

    andiwm2003

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    #4
    to bad that there is this memory bottleneck. even worse it seems to me there is no solution to it short of a complete new design of the logic board/components.:eek:
     
  5. yellow Moderator emeritus

    yellow

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    #5
    I brace myself for the "Apple sucks because my 8-core doesn't download porn faster" threads.
     
  6. sdhollman thread starter macrumors regular

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    #6
    Well that would be the network card would it not? Besides you could download a different porn movies on each proc. :p
     
  7. Pressure macrumors 68040

    Pressure

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    #7
    Their source "thinks" it's a memory bottleneck.

    It could be many factors, the front side bus that becomes saturated with 8-cores and the fact that there is only one 1333Mhz bus for each processor.

    Also have in mind that Clowertown is just two Conroe cores placed on the same package, they do not get access to more bandwidth.

    Adding more cores with the current design is not giving you a linear performance improvement either.

    I also find the lack of benchmarks and testing annoying but they just got it. There are specialized tasks where the 8-core will come to its rights and let it flex its muscles.
     
  8. macenforcer macrumors 65816

    macenforcer

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    Wow, that really stinks. So we have to now wait for a complete architecture redesign so each core gets its own lane. Wow, that could take a while.
     
  9. yellow Moderator emeritus

    yellow

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    #9
    That's the point. FUDtards™ are everywhere.
     
  10. keysersoze macrumors 68000

    keysersoze

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    As long as Safari is snappier, I will be happy.

    :p
     
  11. dartzorichalcos macrumors 65816

    dartzorichalcos

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    They should test a maxed out PowerMac G5 Quad against the 8 core Mac Pro.
    That 8 core Mac Pro is very impressive but I will wait for the next update at least before I buy another mac.
     
  12. dornoforpyros macrumors 68040

    dornoforpyros

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    #12
    So in other words, an 8-core machine is more about bragging rights than of having any actual use to anyone just yet as the software hasn't caught up.

    Meh, I'll stick with my dual-core thanks.
     
  13. Anonymous Freak macrumors 601

    Anonymous Freak

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    #13
    There is a Xeon redesign coming in a couple years with a new serial front side bus more similar to the HyperTransport bus used by AMD than the current one. This should help alleviate some of the bandwidth issues.

    But as we go to massively multicore systems (Intel has in the roadmap a 16-core with hyperthreading chip for late 2008 already,) we'll have to completely re-think how the processor talks to memory. I mean, four cores on one chip already can end up starving the cores for memory bandwidth, even at 1.33 GHz/64-bit. It will only get worse with more cores. Even if Intel bumps their current FSB to 2 GHz, it won't be enough.

    That is what the real purpose of Intel's "80-core" chip was. Not to make an ultra-high-core chip, but to investigate new ways of connecting them. This chip had 80 processing cores, but more importantly, each core had its own connection 'upward' out of the chip. This could allow for a second layer on top containing memory. We might just stack memory right on top of the processor.

    For reference, the theoretical maximum bandwidth from each socket to the northbridge is 10.6 GB/s. (Combined 21.3 GB/s for both chip sockets.) By comparison, the maximum theoretical bandwidth from the memory subsystem to the northbridge is 21.3 GB/s. However, this can only be achieved with memory in all four channels, and is best achieved with only ONE module in each of the four channels. And, this is only 'theoretical' maximum. The serial nature of Fully Buffered memory means that actual bandwidth can be noticeably lower. Testing on other sites has shown that quad-channel FB-DIMMs at 667 MHz (theoretical 21.3 GB/s,) can barely outperform dual-channel conventional DDR-2 800 MHz memory (theoretical max 12.8 GB/s.) And conventional DDR-2 at 1066 MHz (theoretical max 17 GB/s,) seems to reliably outperform FB-DIMMs.
     
  14. PCtoMac-change macrumors member

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    #14
    It seems like just yesterday that dual-core was a dream come true.
     
  15. macenforcer macrumors 65816

    macenforcer

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    #15
    LOL. I was saying the same thing yesterday. Glad I got the Quad 2.66 though. I think even now that is the best machine for the money.
     
  16. twoodcc macrumors P6

    twoodcc

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    #16
    well hopefully Leopard will take full advantage of all the cores....not sure what to say about the memory though.....i wonder what would have happened if apple would have stayed PPC and adopted the Cell processor?
     
  17. nuckinfutz macrumors 603

    nuckinfutz

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    #17
    Apple would have been in a world of hurt. CELL is great for for media tasks due to the multi-core SPE but it's not a replacement for today's general CPU.

    Today's Octo Mac Pro is still beneficial to those who have apps that are CPU bound. Note that renders in Cinema4D smoke. However memory bandwidth doesn't come close to the theoretical spec and it is futher worsened by Tigers lack of core affinity meaning that a thread might load up Core 1's cache and then aquiesce only to start up again on Core 4. Ooops if it jumps to a Core that doesn't share cache you've just wasted time and resources.

    Leopard should keep tasks locked to cores and Intel is always working on improving cach hit rate.

    Nehalem will be a 8-Core proc with 16 possible threads via simultaneous multithreading. In addition to this Intel will incorporate a GPU right in the package in some models along with an Integrated Memory controller. NICE.
     

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