Was reading an article, and got me thinking. Is there an internal bottleneck with Broadwell / Skylake processors that prevent two ports from being added? I'm aware of the space limitations in the device, just curious. I know that the Macbook's USB-C port is 5 Gbps. But with the Google Pixel C (with two USB-C ports), there is some confusion about the true speed of the ports. Despite being USB-C, they may only support USB 2.0 speeds apparently. I know that to get TB3 support on Skylake, it would have required an Alpine Ridge controller. But making sense of all of this, would it have been theoretically possible to support two USB-C ports at 5 Gbps with the standalone Skylake processor?