Rambus doesn't "suck" it was just too expensive. It wasn't until quite recently that (old PC-1066) RDRAM was surpassed by (new PC3200) Dual Channel DDR in terms of performance. Before that, Rambus has always held the performance crown on the P4 platform.
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"Crippled" DDR on new G5's?
- Thread starter erockerboy
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If anything, the DDR I based 400MHz is pretty leading edge in memory technology. Ask the former Apple developer and HW tester why he/she is a former Apple developer and HW tester. 
DDR-II is a completely different beast. Its definitely a year out, even more. As it is, DDR-II dimms won't even fit in the DDR-I slots.
DDR-II is a completely different beast. Its definitely a year out, even more. As it is, DDR-II dimms won't even fit in the DDR-I slots.
This is not 100% true. Rambus has a faster total throughput, but the latency is much higher than DDR, so short operations are much slower. Now that dual DDR is approaching 1ghz. (2x 500), there is no reason to buy the much slower overall and more expensive RDRAM 1066 sticks.
I realize that and was commenting on a previous posters comments on the top of the line Dell they just got.
illumin8:
Interestingly, a very similar thing can be said about the high clocking FSB's on the G5's. Higher throughput than anyone else, but possibly the highest latency around too (although such things are hard to know for sure based on the limited infromation available).
DDR-1 is hardly approaching 500mhz in the mainstream system RAM market. Its definately not a standard, and I'm unaware of any plan to make DDR-1 above 400mhz into a standard.
Wait a sec....Apple's implmentation of DDR isn't crippled. You have to install the RAM in 2's in order to saturate the FSB- eg. 2 x 6.4 G/s = 12.8 G/s (am I correct? )
So all this new DDR implementation is just a movement to a 128-bit archetecture, something that wasn't available when Apple designed the board. I'm pretty sure the new DDR will be put in when Apple cranks up the machines to beyond 2 ghz, most likely (in my opinion) when they get to 3 ghz.
So all this new DDR implementation is just a movement to a 128-bit archetecture, something that wasn't available when Apple designed the board. I'm pretty sure the new DDR will be put in when Apple cranks up the machines to beyond 2 ghz, most likely (in my opinion) when they get to 3 ghz.
MacBandit:
Oops, didn't mean to tell you things you already knew. But anyway, not that I mean to carry such a minor arguement too far, but I just checked at Dell's site and apparently of the 5 models of PC for "home" use, the top 4 all have dual channel DDR RAM, the top two (Dimention XPS and 8300) being dual DDR-400 and a 800mhz FSB. I must say that I'm suprised to see just how dominant dual DDR is in their lineup.
Oops, didn't mean to tell you things you already knew.
But anyway, not that I mean to carry such a minor arguement too far, but I just checked at Dell's site and apparently of the 5 models of PC for "home" use, the top 4 all have dual channel DDR RAM, the top two (Dimention XPS and 8300) being dual DDR-400 and a 800mhz FSB. I must say that I'm suprised to see just how dominant dual DDR is in their lineup.
One thing that's being forgotten in all of this is the G5's use of direct memory access (DMA) technology. Every component has an independent 6.4 GB/s bus to the RAM banks. That takes a LOT of stress off of the system controller, which normally has ALL RAM operations routed through it.
I did the math, and your math is impeccable, albeit for the wrong reasons. While it's true that the RAM controller will access two banks of SDRAM at once, the controller still only moves 128 bits of data at a time. By my math, that's (128/8)*400 000 000 * 2, which should be 12.8 GB/s. I'm not sure why it's not.
The other thing is that the ability to read/write to two banks at a time has little to do with data speeds--the bus can only handle so much regardless. It seems like it would instead reduce latency. I had a good idea going for why, but it escaped me. Hopefully somebody else can prove/disprove my thought.
As for one of the original complaints that 64-bit memory addressing should mean much more memory is addressable--the problem with that idea is the fact that a 22-bit initialization vector needs to be appended to the address, leaving 42 bits to actually address a RAM location.
I did the math, and your math is impeccable, albeit for the wrong reasons. While it's true that the RAM controller will access two banks of SDRAM at once, the controller still only moves 128 bits of data at a time. By my math, that's (128/8)*400 000 000 * 2, which should be 12.8 GB/s. I'm not sure why it's not.
The other thing is that the ability to read/write to two banks at a time has little to do with data speeds--the bus can only handle so much regardless. It seems like it would instead reduce latency. I had a good idea going for why, but it escaped me. Hopefully somebody else can prove/disprove my thought.
As for one of the original complaints that 64-bit memory addressing should mean much more memory is addressable--the problem with that idea is the fact that a 22-bit initialization vector needs to be appended to the address, leaving 42 bits to actually address a RAM location.
They make the simplest math confusing.
There's a reason they call DDR400 memory PC3200.
If the memory controller is looking at two banks of the stuff PC3200 & PC3200 -- it magically equals Apple's estimate of GB/s, imagine that.
Also the reason for needing memory in matched pairs.
There's a reason they call DDR400 memory PC3200.
If the memory controller is looking at two banks of the stuff PC3200 & PC3200 -- it magically equals Apple's estimate of GB/s, imagine that.
Also the reason for needing memory in matched pairs.
Sun Baked-
I didn't multiply by two because the controller reads from two banks at once--I multiplied by two because the controller transfers data on both the rise and the fall of its clock cycle.
(128/8) to convert from bits to bytes...
Multiply by 400 000 000 because that's the clock frequency of the memory controller...
Multiply by two because the controller transfers data on the rise and fall of the clock.
Which works out to 12.8 GB/s. There must be something I'm missing.
I didn't multiply by two because the controller reads from two banks at once--I multiplied by two because the controller transfers data on both the rise and the fall of its clock cycle.
(128/8) to convert from bits to bytes...
Multiply by 400 000 000 because that's the clock frequency of the memory controller...
Multiply by two because the controller transfers data on the rise and fall of the clock.
Which works out to 12.8 GB/s. There must be something I'm missing.
Ahh, but it is, the fact that Rambus has a faster total throughput allows it to keep up with fast FSB's (like the G5's and at it's time the P4's) better than DDR. This was largely the case with the P4 where systems equipped with PC1066 RDRAM consistently outperformed equivalent systems equipped with DDR333/266 SDRAM. I'm afraid you won't find anything in my post that isn't true, i850e/PC1066 RDRAM was Intel's flagship chipset/memory until the arrival of Dual Channel DDR solutions. RDRAM doesn't suck, it only needs a cpu who's FSB is fast enough to take advantage of it's strength (but not that of DDR). Morale of the story, if DDR is fast enough for your cpu's FSB, stick with DDR, if it's not and you have deep pockets, move to Rambus.
Daveman Deluxe:
SDRAM/DDR processes information in 64 bit data paths, I think the reason Apple said 128 bit DDR400 was to signify that it was dual channel. Either that or the G5's using (proprietary?) memory thats unavailable anywhere else in the industry.
SDRAM/DDR processes information in 64 bit data paths, I think the reason Apple said 128 bit DDR400 was to signify that it was dual channel. Either that or the G5's using (proprietary?) memory thats unavailable anywhere else in the industry.
I remember reading an article about RAM some 3 months ago, and they didn't like DDR400, because it was 1.) expensive, and 2.) only showed improvement in certain areas.
They still recommend slower RAM, because DDR400 is still new, and expensive
When BestBuy starts to advertise DDR400 memory in their ads, or even carry the stuff in their stores, then it'll be old.
Besides, rambus is expensive. If Apple were to add it anytime soon, the G5's cost would probably go up a good $500, and don't expect to buy any memory for cheap, especially from Apple.
They still recommend slower RAM, because DDR400 is still new, and expensive
When BestBuy starts to advertise DDR400 memory in their ads, or even carry the stuff in their stores, then it'll be old.
Besides, rambus is expensive. If Apple were to add it anytime soon, the G5's cost would probably go up a good $500, and don't expect to buy any memory for cheap, especially from Apple.
Cubeboy:
Although the terms get misused a lot (by myself even), the difference between one 128-bit memory channel and 2 64-bit channels is in how they can be accessed. Dual channel implies that memory can be read separately on each channel, 128-bit implies that that they operate as one (they share address lines). I think most times people say dual-channel they really mean 128-bit, and not two imdependent 64-bit channels.
Although the terms get misused a lot (by myself even), the difference between one 128-bit memory channel and 2 64-bit channels is in how they can be accessed. Dual channel implies that memory can be read separately on each channel, 128-bit implies that that they operate as one (they share address lines). I think most times people say dual-channel they really mean 128-bit, and not two imdependent 64-bit channels.
That's good to know, but the fact remains that data will still travel 128 bits at a time, twice for each clock cycle. Unless I'm missing something important about how dual-channel actually works, my math stands.
You are missing something. Each bank is only 64bits wide so it should be
64/8 to get 8 bytes/cycle
multiply by 400 000 000 cycles and then by 2 (2 banks) to get 6.4Gb/s
Or, you could've just multiplied the 3200 in PC3200 by 2 and reached that much faster.
The 400 in DDR400 stands for the megahertz of the ram, while the 3200 in PC3200 stands for the throughput (in mb) of the ram.
Hope I cleared everything up
Originally posted by ddtlm
MacBandit:
Oops, didn't mean to tell you things you already knew.
Hey no problem. I didn't know about the current lineup of top end Dells. That's cool for the industry. I would say this is pretty new though probably just since the introduction of the 800MHz FSB P4s.
RAMBUS = CRAP
I also had a terrible experience with RAMBUS at work. we needed a really fast machine for some computing intense stuff and some guys decided to go with one RAMBUS based. WTF'g piece of crap. I could not believe it. I have never seen a computer so unstable in my life, not a Mac, not a PC.
I also had a terrible experience with RAMBUS at work. we needed a really fast machine for some computing intense stuff and some guys decided to go with one RAMBUS based. WTF'g piece of crap. I could not believe it. I have never seen a computer so unstable in my life, not a Mac, not a PC.
The DDR is fine. This guy sounds just dangerous enough with his misinformation to do damage.
The G5 Dual 2Ghz is not using the full bandwidth available. Each FSB to the processor could consume the whole 6.4GBps throughput. Unfortunately while each processor has it's own FSB they both meet the Memory controller which "talks" to the bank of DDR so you're halving the memory anyways.
The ideal situation would be either 2 Dual channel banks of RAM with two system controllers or ondie memory controllers. But we're talking alot more $$$ if you doubled the ram slots and added a beefier controller.
The statements on Altivec are just plane false. You don't have to recompile because the Altivec unit is the same as the 7400 chip. The G4+ had a slightly tweaked unit but they all function the same. Where the optimizations will likely be is taking advantage of the inflight intruction advantage and out of order execution benefits of the G5.
Perhaps the PPC 980(mythical) will have a improved Altivec unit but it may not as the dual FPU units will provide a nice boost to apps recompiled to take advantage.
The G5 Dual 2Ghz is not using the full bandwidth available. Each FSB to the processor could consume the whole 6.4GBps throughput. Unfortunately while each processor has it's own FSB they both meet the Memory controller which "talks" to the bank of DDR so you're halving the memory anyways.
The ideal situation would be either 2 Dual channel banks of RAM with two system controllers or ondie memory controllers. But we're talking alot more $$$ if you doubled the ram slots and added a beefier controller.
The statements on Altivec are just plane false. You don't have to recompile because the Altivec unit is the same as the 7400 chip. The G4+ had a slightly tweaked unit but they all function the same. Where the optimizations will likely be is taking advantage of the inflight intruction advantage and out of order execution benefits of the G5.
Perhaps the PPC 980(mythical) will have a improved Altivec unit but it may not as the dual FPU units will provide a nice boost to apps recompiled to take advantage.
There are a few vector cache touch instructions (DCBsomething) that are slow on the G5 and should be avoided, but overall it has shown (in benchmarks) to be roughly equivalent per clock to the G4 on vector code.
acj, you do have a point - I simply did not say that after we bought our Rambus pc, we heard of many others having a bad experience with it. It was not just our PC that was crap. Still, I am not stating that this constitutes statistical evidence. However I am implying that MY experience has been crap. And in professonal computing world you may very well understand that individual experiences are often all it takes to determine one's feeling towards a product. And my feeling remains, it is crap.
In any event, I am glad your particular experience has been so good.
In any event, I am glad your particular experience has been so good.
I worked at a company, which will remain nameless, and we had unending troubles with rambus. It was one of my duties to every monday at 9 A.M. to replace the rambus in our servers that died over the weekend, which it always, without fail, did. At least four design computers on our floor had their rambus smoke every week. It cost said company at least $10,000 dollars a week in rambus; this is no exaggeration. Pleading with management to get new computers was wasted effort as it would make them look like they had made a mistake in ordering them. Eventually one of the sticks of rambus fused to its slot and we got a new enterprise server. One down 11 to go.
Moral of the story bleeding edge is not always the best place to stand. DDR 400 is out it works and it is fast.
Moral of the story bleeding edge is not always the best place to stand. DDR 400 is out it works and it is fast.
makes my late celeron with PC66 look a bit old dont it?
makes an emac with only PC100 look a bit slow dont it?
makes a DP G5 with DDR400 dual channel RAM and all that 64bit stuff look like a good buy. now here do they put the monitor??????
really, i know my sh:t but i also know that the faster the FSB is and the faster the RAM is the faster the rest of the system will perform asa general rule.