And yet that was not my question. I knew about CISC running parallel instructions - I was inquiring about the same process on a RISC architecture.
It’s also not quite the same process in CISC. In CISC, imagine you have an instruction:
ADD [Contents of memory A], [Contents of memory B] -> Memory C + value in R2
This gets decoded into a set of instructions:
1) LOAD A -> temp register 1
2) LOAD B -> temp register 2
3) ADD temp register 1, temp register 2 -> temp register 3
4) LOAD C -> temp register 4
5) ADD temp register 4, R2 -> temp register 5
6) STORE temp register 3 -> [address corresponding to temp register 5]
Now imagine this occurs right after an instruction like “if x==4 then...”
So do we issue these instructions or not? We don’t want to wait to figure out if x is 4, so we guess. If we guess wrong, we have to unwind all the work done in 1-6. Which means we need to keep track of the fact that 1-6 all correspond to a single “add” instruction.
We also have to deal with the temp register assignments. In instruction (4), can we use temp register 1 instead of 4? Maybe. It depends on whether (3) has already issued. How do we decide which temp registers to use? There are a finite number, and we want to be as clever as possible so we don’t stall while waiting for them to free up.
it gets *very* complicated. Much more so than RISC.