The official Apple schematic only shows BOM options for bus speeds from 133MHz to 200MHz. However, I have a suspicion that bus speeds up to 300MHz (well, 291MHz to be exact) are possible. Why? In the schematic, when MAXBUS_D44 is set to 1, the bus speed is set 50% higher than is MAXBUS_D44 is set to 0. The schematic only shows the 200MHz, or 133MHzx1.5, option, but I think it is possible to use MAXBUS_D44 to create a bus speed of 291MHz, or 194MHzx1.5. If possible, a 300MHz bus speed would be set by placing 10K-Ohm resistors at positions R2304, R2306, R2308, and R2310, while ensuring that there are no resistors present at locations R2305, R2307, R2309, and R2311. One must also set an appropriate bus-to-core ratio, because the stock multiplier would set the processor much too fast. I am planning on taking the PowerBook to a facility that can resolder the SMT resistors needed to set this bus speed, and I will post back the results when and if I get the job done.