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Equivalent of AGDCDiagnose with apple silicon macs?

T

toke lahti

macrumors 68040
Original poster
In the past info about video connection to a display told about bit depth and chroma subsampling in System Information.
Not any more.

How to get that info?

I need to verify is my mac driving my tv in RGB or YCbCr.
The tv (UE49KU6645) does not tell that.
I want to calibrate the tv properly and it should be done with same format that my mac will use with it.
 
ioreg can show a list of display modes (TimingElement) and a list of color modes (ColorElement) for each display mode. It shows which display mode is being used but doesn't show which color mode is being used?
I think AllRez can dump all the info from ioreg https://github.com/joevt/AllRez but it's not formatted well.
The information from ioreg can be parsed using the info at
https://forums.macrumors.com/threads/diy-5k-monitor-success.2253100/post-32093817
Hmm - where's the DSC target bits per pixel? It's usually 12 bpp but can be lower on Apple Silicon Macs. A patch is required for Intel Macs to change the dscTargetBPP preference.
With Intel Macs, a DetailedTimingInformation in AllRez includes the output color info for the display mode and the DSC target bits per pixel.

I would look for hidden APIs that can return the info for Apple Silicon Macs.

Have a look at @waydabber 's BetterDisplay.app. It has a command line interface. Does the following command list all the timing elements and color elements per timing element? I haven't tried it since I don't have an Apple Silicon Mac.
Code: 
betterdisplaycli get -n=DISPLAYNAME -connectionModeListAll

I'm not sure if BetterDisplay is describing framebuffer color info or output color info.
 
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Hi all, this command lists timings and connection level color mode elements macOS deems viable (based on the EDID and available bandwidth), so it's not about framebuffer color representation options.

The

Code: 
betterdisplaycli get -n=DISPLAYNAME -connectionMode

will show the current configuration, for example:

Code: 
11929753937963126528 - 3840x2160 120.00Hz Variable 10bit SDR YCbCr 4:4:4 Limited SRGB

One can switch to a mode using `set` and `connectionMode=<identifier>`

The app's Color Mode menu also lists current and available options for the current timing and provides a way to switch easily.

For example:

Screenshot 2025-11-05 at 10.50.18.png
 
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BetterDisplay (app) is great!
Much easier to find possible combinations than command line!

@waydabber, Feature suggestion:
In BD, we could have the signal specs visible at all times (optionally of course) in the bottom of the dropdown menu or in own window or popup-menu:
  1. Resolution
  2. Refresh rate
  3. Bit depth
  4. RGB / YCbCr
  5. Chroma subsampling
  6. SDR / HDR
  7. Full / limited range
  8. HiDPI
  9. Maybe even a pixel clock? (MHz)
I just had an extensive cable testing with my M1pro-mbp with this Samsung TV.
Turns out, that with amazonBasics dp-hdmi cable with fullDP-usbc adapter, I can get 3840x2160, 60Hz, 10bit, RGB (4:4:4), HDR10, full range.

From mbp's hdmi output I can only get 30Hz.

And with cheapo "jsaux" hdmi-usbc adaptor (printed 4kUHD on it...) same 30Hz, but not even HDR!

And now I can continue to calibrate the tv with simple combination of:
  1. RP4
  2. PgenOS
  3. windows laptop
  4. Pg_client / HCFR
Sadly, seems to be, that all my cheap hdmi switchers are limited to 300 MHz pixel clock...
 
Last edited:
waydabber said:
so it's not about framebuffer color representation options
Click to expand...
Is there a separate command line or UI for framebuffer color representation?
Could there be a situation where framebuffer is 10bpc RGB but is output to 8bpc 4:2:2 (using dithering) or similar color transformations?
 
joevt said:
Is there a separate command line or UI for framebuffer color representation?
Could there be a situation where framebuffer is 10bpc RGB but is output to 8bpc 4:2:2 (using dithering) or similar color transformations?
Click to expand...

There is a separate display mode list `get -displayModeList`, which will show the framebuffer color depth, but for natively connected displays that is almost always 10bpc. For more detailed data for the current mode one can look the "Current Display Mode" section under Display Information….

The framebuffer bit depth and connection color mode bit depth can be different. Apple Silicon Macs can simply downscale the color depth or bridge the gap using GPU dithering (this can actually be toggled for some connections by changing the relevant framebuffer ioreg property which the DCP – the thing in the Apple Silicon chip that actually creates the output signal from the framebuffer – seems to honor instantly).

The app can't query the possible or actual DSC average payload per pixel (although this can be calculated from the available bandwidth) - as for the DSC target bpp I think it is (or should be) the same as the color mode's bit depth. But I may have my terminology wrong. 🙂
 
How do you get available bandwidth?

I think the color mode bit depths are bpc while DSC target is bpp.
You can have 10 bpc (30 bpp) compressed to 12 bpp (the default) or even 8 bpp (for when 12 bpp is not enough compression).
 
Yes, you are right.

When a display connects the following info can be intercepted from `AppleDCPDPTXController` (this is an example for a TV connecting at 4K@120Hz).

Code: 
AppleDCPDPTXController::validateVideo Validating link @ 4 lanes and 8100000000Gbps
AppleDCPDPTXController::validateVideo Color: depth=10bpc encoding=3 [YCbCr 4:4:4] range=1 [Limited] colorimetry=1 [BT.709]
AppleDCPDPTXController::validateVideo Horizontal: total=4400 frontPorch=176 syncWidth=88 backPorch=296 active=3840
AppleDCPDPTXController::validateVideo Vertical: total=2250 frontPorch=8 syncWidth=10 backPorch=72 active=2160 syncRate=60.0000Hz
AppleDCPDPTXController::validateVideo Timing: pixelClock=594000000 interlaced=0 split=0
AppleDCPDPTXController::validateVideo Link: usableLinkBandwidth=25312113767bps < totalLinkBandwidth=25920000000bps
AppleDCPDPTXController::validateVideo Link: dsc=NO dsc.bpp=0.0000 videoBandwidth=17820000000bps usableBandwidth=25312113767bps
AppleDCPDPTXController::getBandwidthRatio videoBandwidth=17820000000bps linkBandwidth=25920000000bps bandwidthRatio=0.6875

Notice the connection level mode info, DSC use and DSC BPP (it should be specified there if DSC is in use, in this example it is not), the usable and bandwidth required bandwidth (`videBandwidth`) and the resulting bandwidth ratio for this video mode.

Also various other details can be intercepted from the negatioation process and even link training details.
 
waydabber said:
Yes, you are right.

When a display connects the following info can be intercepted from `AppleDCPDPTXController` (this is an example for a TV connecting at 4K@120Hz).

Code: 
AppleDCPDPTXController::validateVideo Validating link @ 4 lanes and 8100000000Gbps
AppleDCPDPTXController::validateVideo Color: depth=10bpc encoding=3 [YCbCr 4:4:4] range=1 [Limited] colorimetry=1 [BT.709]
AppleDCPDPTXController::validateVideo Horizontal: total=4400 frontPorch=176 syncWidth=88 backPorch=296 active=3840
AppleDCPDPTXController::validateVideo Vertical: total=2250 frontPorch=8 syncWidth=10 backPorch=72 active=2160 syncRate=60.0000Hz
AppleDCPDPTXController::validateVideo Timing: pixelClock=594000000 interlaced=0 split=0
AppleDCPDPTXController::validateVideo Link: usableLinkBandwidth=25312113767bps < totalLinkBandwidth=25920000000bps
AppleDCPDPTXController::validateVideo Link: dsc=NO dsc.bpp=0.0000 videoBandwidth=17820000000bps usableBandwidth=25312113767bps
AppleDCPDPTXController::getBandwidthRatio videoBandwidth=17820000000bps linkBandwidth=25920000000bps bandwidthRatio=0.6875

Notice the connection level mode info, DSC use and DSC BPP (it should be specified there if DSC is in use, in this example it is not), the usable and bandwidth required bandwidth (`videBandwidth`) and the resulting bandwidth ratio for this video mode.

Also various other details can be intercepted from the negatioation process and even link training details.
Click to expand...
That's great info. You mention how to see AppleDCPDPTXController using the log show command in the BetterDisplay Discord.

dsc.bpp has a decimal point because it can be specified in 16ths of a pixel.
10 bpc = 30 bpp.
videoBandwidth is pixelClock*bpp = 594 MHz * 30 bpp = 17.82 Gbps.
linkBandwidth is 4 lanes * 8.1 GTps * 8b/10T = 25.92 Gbps.
bandwidthRatio is videoBandwidth / linkBandwidth = 17.82 / 25.92 = 68.75%

I don't know what usableLinkBandwidth is. I wonder what it's accounting for and how it's calculated? Is it for FEC? Usually FEC is used only when DSC is enabled? The timing is HDMI but the link is 4 lanes of DisplayPort HBR3. Is there a MST hub in the chain?
usableLinkBandwidth is 97.6547599035494% of totalLinkBandwidth.
totalLinkBandwidth is 1.024015625032174% of usableLinkBandwidth.
The difference is 607886233 which is 2.4015625032174% of usableLinkBandwidth or 2.3452400964506% of totalLinkBandwidth.
 
> You mention how to see AppleDCPDPTXController using the log show command in the BetterDisplay Discord.

Yes, one can use this command to get kernel logs related to anything "DCP" (the component of the Apple Silicon chip that manages display connections and produces the actual video signal from the framebuffer).

Code: 
log show --last 2m --info --predicate "processImagePath CONTAINS 'kernel' AND senderImagePath CONTAINS 'DCP'"

> Is there a MST hub in the chain?

AppleSilicon outputs DP only I think, but this particular connection was using an M3 Max MBP's HDMI port (connected to an LG OLED TV). Afaik there is a Parade DisplayPort to HDMI protocol converter chip built into the MacBook that's doing the conversion.
 
I am sure there is a better way but to be honest, I did not research the topic any further. Let us know if you figure something out!
 
joevt said:
That MacBook Pro sends DP through USB-C and your cable converts it to HDMI.
Click to expand...
I don't believe that such a cheap cable can do that @4k60.
Usually those conversion boxes cost 10x and need eternal power.

I belive it is a passive cable. Those active one's are way more expensive.
Would be nice to be wrong, though.

Any evidence?
 
toke lahti said:
I don't believe that such a cheap cable can do that @4k60.
Usually those conversion boxes cost 10x and need eternal power.

I belive it is a passive cable. Those active one's are way more expensive.
Would be nice to be wrong, though.

Any evidence?
Click to expand...
I don't know if anyone implements USB-C HDMI Alternate Mode.
If the cable required USB-C HDMI Alternate Mode (for passive HDMI) then that would greatly reduce the compatibility of the cable.

If you connect the cable to an Intel Mac, then you could get the DPCD info from the DisplayPort device in the cable using AllRez. It would tell us which DisplayPort to HDMI adapter it uses.
 
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joevt said:
I don't know if anyone implements USB-C HDMI Alternate Mode.
If the cable required USB-C HDMI Alternate Mode (for passive HDMI) then that would greatly reduce the compatibility of the cable.

If you connect the cable to an Intel Mac, then you could get the DPCD info from the DisplayPort device in the cable using AllRez. It would tell us which DisplayPort to HDMI adapter it uses.
Click to expand...
Okay,
I did run the command with M1-mbp with macOS 14.
Pages tell me that the resulting text file has 838889 characters without spaces.
820 pages.

Could you help with a search word?
HDMI is mentioned only once:
Code: 
HasHDMILegacyEDID = 0;
 
toke lahti said:
Okay,
I did run the command with M1-mbp with macOS 14.
Pages tell me that the resulting text file has 838889 characters without spaces.
820 pages.

Could you help with a search word?
HDMI is mentioned only once:
Code: 
HasHDMILegacyEDID = 0;
Click to expand...
AllRez does not have code to get DPCD info on a Apple Silicon Mac. The API doesn't exist or is not documented. In the latter case, one could try to find a suitably named function, then try and guess how to use the function.
You can zip the results and post here for us to look at.
 
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joevt said:
AllRez does not have code to get DPCD info on a Apple Silicon Mac. The API doesn't exist or is not documented. In the latter case, one could try to find a suitably named function, then try and guess how to use the function.
You can zip the results and post here for us to look at.
Click to expand...
I did the same with my mini2018.
Should it be run from terminal with some swithces to show just what we are looking for?
Now I got 1M characters ≈ 377 pages.
DPCD appears 58 times, what am I looking for?
 
toke lahti said:
I did the same with my mini2018.
Should it be run from terminal with some swithces to show just what we are looking for?
Now I got 1M characters ≈ 377 pages.
DPCD appears 58 times, what am I looking for?
Click to expand...
If you zip the file, it will compress to a more reasonably sized file that you can attach to a post.

The interesting stuff is probably between these lines:
Code: 
                DisplayPort = {
                    dpcd = {
....
                    }; // dpcd
                }; // DisplayPort

I think for identifying HDMI adapters, you want to look at the sink and branch OUI and ID lines like these:
Code: 
BRANCH_OUI: 00-0C-6C = Eve Systems GmbH
BRANCH_OUI: 00-10-FA = Apple, Inc.
BRANCH_OUI: 00-1C-F8 = Parade Technologies, Ltd.
BRANCH_OUI: 00-60-AD = MegaChips Corporation
BRANCH_OUI: 00-80-E1 = STMicroelectronics SRL
BRANCH_OUI: 12-14-C4 = Unknown OUI
BRANCH_OUI: 90-CC-24 = Synaptics, Inc
BRANCH_ID: 01 01 00 01 80 02 // ......
BRANCH_ID: 31 37 36 47 42 30 // 176GB0
BRANCH_ID: 44 70 31 2e 32 00 // Dp1.2.
BRANCH_ID: 45 6c 67 54 42 44  ElgTBD
BRANCH_ID: 45 6c 67 54 42 44 // ElgTBD
BRANCH_ID: 4d 43 32 39 30 09 // MC290.
BRANCH_ID: 53 59 4e 41 33 32 // SYNA32
BRANCH_ID: 53 59 4e 41 52 00 // SYNAR.
BRANCH_ID: 53 59 4e 41 53 22 // SYNAS"
BRANCH_ID: 53 59 4e 41 53 31 // SYNAS1
BRANCH_ID: 53 59 4e 41 61 00 // SYNAa.
BRANCH_ID: 53 59 4e 41 71 00 // SYNAq.
BRANCH_ID: 6d 32 44 56 49 61 // m2DVIa
BRANCH_ID: 70 48 44 4d 49 66  pHDMIf
BRANCH_ID: 70 48 44 4d 49 66 // pHDMIf
SINK_OUI: 00-0C-E7 = MediaTek Inc.
SINK_OUI: 00-10-FA = Apple, Inc.
SINK_OUI: 00-14-B9 = MSTAR SEMICONDUCTOR
SINK_OUI: 00-1B-C5 = IEEE Registration Authority
SINK_OUI: 00-80-E1 = STMicroelectronics SRL
SINK_OUI: 00-E0-4C = REALTEK SEMICONDUCTOR CORP.
SINK_OUI: 12-14-C4 = Unknown OUI
SINK_OUI: 38-EC-11 = Novatek Microelectronics Corp.
SINK_OUI: 47-53-53 = Unknown OUI
SINK_OUI: E8-5B-5B = LG ELECTRONICS INC
SINK_ID: 00 00 01 01 00 01 // ......
SINK_ID: 00 0c e7 00 00 00 // ......
SINK_ID: 01 01 00 01 80 02 // ......
SINK_ID: 33 34 47 4e 38 35  34GN85
SINK_ID: 41 34 34 36 30 32  A44602
SINK_ID: 41 42 43 44 45 46 // ABCDEF
SINK_ID: 41 47 36 33 32 30 // AG6320
SINK_ID: 44 70 31 2e 32 00 // Dp1.2.
SINK_ID: 44 70 31 2e 34 00 // Dp1.4.
SINK_ID: 4c 47 45 4d 4e 54 // LGEMNT
SINK_ID: 4d 4e 32 32 67 31 // MN22g1
SINK_ID: 4d 4e 32 37 64 33  MN27d3
SINK_ID: 4d 4e 32 37 68 31 // MN27h1
SINK_ID: 4d 4f 4e 32 34 00 // MON24.
SINK_ID: 4d 4f 4e 32 37 61 // MON27a
SINK_ID: 4e 54 36 00 00 00 // NT6...
SINK_ID: 65 44 12 61 62 61 // eD.aba
SINK_ID: 65 44 13 63 62 61 // eD.cba
SINK_ID: 65 44 13 64 62 61 // eD.dba
SINK_ID: 65 44 15 63 61 61 // eD.caa
SINK_ID: 65 44 15 65 62 61 // eD.eba
SINK_ID: 65 44 15 67 62 61 // eD.gba
SINK_ID: 65 44 31 31 61 61 // eD11aa
SINK_ID: 65 44 31 35 62 61 // eD15ba
 
I've got 3 "DisplayPort = {" 's.
The 3rd one is the only one with "BRANCH_OUI:" and it's from Apple.

1.
Code: 
DisplayPort = {
                    (69010h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69020h: dpErrReadDpcd result:kIOReturnNotReady)
                    dpcd = {
                        00000h: 14 14 c4 01 01 10 01 00 02 00 04 00 00 00 84 00 // ................
                        00100h: 14 84 00 06 06 06 06 10 00 00 00 00 00 00 00 00 // ................
                        00150h: 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00 00 // ................
                        00200h: 41 00 77 77 01 03 22 22 00 00 00 00 00 00 00 00 // A.ww..""........
                        00210h: 00 80 00 80 00 80 00 80 00 00 00 00 00 00 00 00 // ................
                        00600h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        02000h: 00 00 41 00 00 02 00 00 00 00 00 00 77 77 01 03 // ..A.........ww..
                        02200h: 14 14 c4 01 01 10 01 00 02 00 04 00 00 00 84 00 // ................
                        02210h: 58 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // X...............
                        03050h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        68000h: 4b 9a 9b 51 2e 00 00 00 00 00 00 00 00 00 00 00 // K..Q............
                        68020h: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................
                        692c0h: 2b 92 b4 1c 64 02 86 e2 89 f9 84 9d 69 7a 46 8a // +...d.......izF.
                        692e0h: df 5d c1 10 76 ad 58 67 72 c2 04 18 71 66 59 06 // .]..v.Xgr...qfY.
                        69310h: a5 ba a2 2e 03 c6 bd 5b 00 00 00 00 00 00 00 00 // .......[........
                        f0000h: 14 1e 80 55 04 00 00 00 00 00 00 00 00 00 00 00 // ...U............

                        Receiver Capability
                            00000h DPCD_REV: 1.4
                            00001h MAX_LINK_RATE: HBR2
                            00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                            00003h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5
                            00004h NORP: 2
                            00005h DOWNSTREAMPORT_PRESENT: PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                            00006h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                            00008h RECEIVE_PORT_0_CAP_0: LOCAL_EDID_PRESENT
                            0000ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                            0000eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
                        Link Configuration
                            00100h LINK_BW_SET: HBR2
                            00101h LANE_COUNT_SET: 4, ENHANCED_FRAME_EN
                            00103h TRAINING_LANE0_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_MAX_SWING_REACHED, TRAIN_PRE_EMPH_LEVEL_0
                            00104h TRAINING_LANE1_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_MAX_SWING_REACHED, TRAIN_PRE_EMPH_LEVEL_0
                            00105h TRAINING_LANE2_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_MAX_SWING_REACHED, TRAIN_PRE_EMPH_LEVEL_0
                            00106h TRAINING_LANE3_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_MAX_SWING_REACHED, TRAIN_PRE_EMPH_LEVEL_0
                            00107h DOWNSPREAD_CTRL: SPREAD_AMP_0_5
                            00154h TX_GTC_VALUE: 0x10000000
                        Link/Sink Device Status
                            00200h SINK_COUNT: 1, SINK_CP_READY
                            00202h LANE0_1_STATUS: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            00202h LANE0_1_STATUS: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            00203h LANE2_3_STATUS: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            00203h LANE2_3_STATUS: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            00204h LANE_ALIGN_STATUS_UPDATED: INTERLANE_ALIGN_DONE
                            00205h SINK_STATUS: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
                            00206h ADJUST_REQUEST_LANE0_1: LANE0 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                            00206h ADJUST_REQUEST_LANE0_1: LANE1 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                            00207h ADJUST_REQUEST_LANE2_3: LANE2 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                            00207h ADJUST_REQUEST_LANE2_3: LANE3 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
                            00210h SYMBOL_ERROR_COUNT_LANE0: 0, valid
                            00212h SYMBOL_ERROR_COUNT_LANE1: 0, valid
                            00214h SYMBOL_ERROR_COUNT_LANE2: 0, valid
                            00216h SYMBOL_ERROR_COUNT_LANE3: 0, valid
                        Sink Control
                            00600h SET_POWER: SET_POWER_D0
                        DPRX ESI (Event Status Indicator)
                            02002h SINK_COUNT_ESI: 1, SINK_CP_READY
                            02005h LINK_SERVICE_IRQ_VECTOR_ESI0: K_STATUS_CHANGED
                            0200ch LANE0_1_STATUS_ESI: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            0200ch LANE0_1_STATUS_ESI: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            0200dh LANE2_3_STATUS_ESI: LANE2 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            0200dh LANE2_3_STATUS_ESI: LANE3 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
                            0200eh LANE_ALIGN_STATUS_UPDATED_ESI: INTERLANE_ALIGN_DONE
                            0200fh SINK_STATUS_ESI: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
                        Extended Receiver Capability
                            02200h DP13_DPCD_REV: 1.4
                            02201h MAX_LINK_RATE: HBR2
                            02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                            02203h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5
                            02204h NORP: 2
                            02205h DOWNSTREAMPORT_PRESENT: PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                            02206h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                            02208h RECEIVE_PORT_0_CAP_0: LOCAL_EDID_PRESENT
                            0220ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                            0220eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
                            02210h DPRX_FEATURE_ENUMERATION_LIST: VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED, VSC_EXT_VESA_SDP_SUPPORTED, VSC_EXT_CEA_SDP_SUPPORTED
                        PCON HDMI CONFIG PPS Override Buffer
                            03050h PROTOCOL_CONVERTER_CONTROL_0: HDMI_DVI_OUTPUT_CONFIG
                        HDCP 1.3 and HDCP 2.2
                            68000h AUX_HDCP_BKSV: 4b 9a 9b 51 2e // K..Q.
                            68028h AUX_HDCP_BCAPS: BCAPS_HDCP_CAPABLE
                        DP HDCP 2.2 Parameters
                            692c0h HDCP_2_2_REG_HPRIME: 2b 92 b4 1c 64 02 86 e2 89 f9 84 9d 69 7a 46 8a // +...d.......izF.
                            692e0h HDCP_2_2_REG_EKH_KM_RD: df 5d c1 10 76 ad 58 67 72 c2 04 18 71 66 59 06 // .]..v.Xgr...qfY.
                            69310h : a5 ba a2 2e 03 c6 bd 5b // .......[
                        Link Training (LT)-tunable PHY Repeaters (LTTPR)
                            f0000h LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV: 1.4
                            f0001h MAX_LINK_RATE_PHY_REPEATER: HBR3
                            f0002h PHY_REPEATER_CNT: 128
                            f0003h PHY_REPEATER_MODE: TRANSPARENT
                            f0004h MAX_LANE_COUNT_PHY_REPEATER: 4
                    }; // dpcd
                }; // DisplayPort
2.
Code: 
DisplayPort = {
                    (00000h: dpErrReadDpcd result:kIOReturnNotPermitted)
                }; // DisplayPort
3.
Code: 
DisplayPort = {
                    (69000h: dpErrReadDpcd result:kIOReturnNotReady)
                    (692a0h: dpErrReadDpcd result:kIOReturnNotReady)
                    (692b0h: dpErrReadDpcd result:kIOReturnNotReady)
                    (692f0h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69310h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69320h: dpErrReadDpcd result:kIOReturnNotReady)
                    (693e0h: dpErrReadDpcd result:kIOReturnNotReady)
                    (693f0h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69470h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69490h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69510h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69520h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69530h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69540h: dpErrReadDpcd result:kIOReturnNotReady)
                    (69550h: dpErrReadDpcd result:kIOReturnNotReady)
                    dpcd = {
                        00000h: 14 14 e4 81 01 1d 01 81 28 07 04 00 0c 00 84 00 // ........(.......
                        00080h: 0b f0 03 1f 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        00100h: 00 00 00 00 00 00 00 00 00 40 00 00 00 00 00 00 // .........@......
                        00200h: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 // ................
                        00240h: 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 // ...... .........
                        00300h: 00 10 fa 41 41 50 4c 00 00 01 01 00 00 00 00 00 // ...AAPL.........
                        00500h: 00 10 fa 70 48 44 4d 49 66 14 02 19 c5 00 00 00 // ...pHDMIf.......
                        00510h: 00 00 00 00 00 00 00 00 00 00 04 04 04 04 01 00 // ................
                        00520h: 00 00 00 00 00 00 00 00 00 00 00 00 52 02 00 00 // ............R...
                        00530h: 00 00 00 30 00 00 00 00 00 00 00 00 83 00 00 01 // ...0............
                        00540h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 // ................
                        00550h: 00 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
                        005f0h: 00 00 00 00 00 00 c8 80 00 00 00 00 00 00 00 00 // ................
                        00600h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        00700h: df a0 3c 04 23 a8 76 40 3f bc aa 5d e2 dd 72 25 // ..<.#.v@?..]..r%
                        00720h: 8a 3c a4 1b ca 37 2d 0e 2b fd be 90 cc d2 3d c8 // .<...7-.+.....=.
                        00730h: 6e de e0 c2 64 80 41 b6 16 ad 04 0b 1d d3 6f 05 // n...d.A.......o.
                        02000h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 // ................
                        02200h: 14 14 e4 81 01 1d 01 81 28 07 04 00 0c 00 84 00 // ........(.......
                        02210h: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        03000h: 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        03030h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        03050h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
                        68000h: b0 85 b5 d6 e2 0f 34 00 00 00 00 00 00 00 00 00 // ......4.........
                        68020h: 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 // ................
                        68030h: fd 00 00 00 00 02 03 e5 fd 00 00 00 00 00 00 00 // ................
                        680c0h: 10 00 00 00 00 00 b0 85 b5 d6 e2 00 00 00 00 00 // ................
                        680f0h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0e // ................

                        Receiver Capability
                            00000h DPCD_REV: 1.4
                            00001h MAX_LINK_RATE: HBR2
                            00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED, ?0x20
                            00003h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
                            00004h NORP: 2
                            00005h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DVI or HDMI, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE
                            00006h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                            00007h DOWN_STREAM_PORT_COUNT: 1, OUI_SUPPORT
                            00008h RECEIVE_PORT_0_CAP_0: ?0x28
                            00009h RECEIVE_PORT_0_BUFFER_SIZE: 256 bytes per lane
                            0000ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                            0000ch I2C_SPEED_CAP: 10kbps, 100kbps
                            0000eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
                            00080h DOWNSTREAM_PORT_0: PORT_TYPE = HDMI, HPD aware, 600 MHz max TMDS clock, DS_MAX_BPC = 16bpc, PCON_MAX_FRL_BW = 0Gbps, FRAME_SEQ_TO_FRAME_PACK, YCBCR422_PASS_THROUGH, YCBCR420_PASS_THROUGH, YCBCR444_TO_422_CONV, YCBCR444_TO_420_CONV
                        Link Configuration
                            00109h I2C_SPEED_CONTROL_STATUS: ?0x40
                        Link/Sink Device Status
                            00204h LANE_ALIGN_STATUS_UPDATED: LINK_STATUS_UPDATED
                            00246h TEST_SINK_MISC: TST_CRC_COUNT = 0, TEST_CRC_SUPPORTED
                        Source Device-Specific
                            00300h SOURCE_OUI: 00-10-FA = Apple, Inc.
                            00303h SOURCE_ID: 41 41 50 4c 00 00 // AAPL..
                            00309h SOURCE_HW_REV: 0.1
                            0030ah SOURCE_SW_REV: 1.0
                        Branch Device-Specific
                            00500h BRANCH_OUI: 00-10-FA = Apple, Inc.
                            00503h BRANCH_ID: 70 48 44 4d 49 66 // pHDMIf
                            00509h BRANCH_HW_REV: 1.4
                            0050ah BRANCH_SW_REV: 2.25
                            0050ch : c5 00 00 00 // ....
                            00510h : 00 00 00 00 00 00 00 00 00 00 04 04 04 04 01 00 // ................
                            00520h : 00 00 00 00 00 00 00 00 00 00 00 00 52 02 00 00 // ............R...
                            00530h : 00 00 00 30 00 00 00 00 00 00 00 00 83 00 00 01 // ...0............
                            00540h : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ff 00 // ................
                            00550h : 00 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
                            005f0h : 00 00 00 00 00 00 c8 80 00 00 00 00 00 00 00 00 // ................
                        Sink Control
                            00600h SET_POWER: SET_POWER_D0
                        eDP-Specific
                            00700h EDP_DPCD_REV: ?223 (unknown)
                            00701h EDP_GENERAL_CAP_1: EDP_FRC_ENABLE_CAP, EDP_SET_POWER_CAP
                            00702h EDP_BACKLIGHT_ADJUSTMENT_CAP: EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT, EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP, EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP, EDP_BACKLIGHT_FREQ_AUX_SET_CAP
                            00703h EDP_GENERAL_CAP_2: ?0x04
                            00704h EDP_GENERAL_CAP_3: EDP_X_REGION_CAP = 3, EDP_Y_REGION_CAP = 2
                            00705h : a8 76 40 3f bc aa 5d e2 dd 72 25 // .v@?..]..r%
                            00720h EDP_DISPLAY_CONTROL_REGISTER: EDP_BLACK_VIDEO_ENABLE, EDP_COLOR_ENGINE_ENABLE, EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE
                            00721h EDP_BACKLIGHT_MODE_SET_REGISTER: PWM, EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE, EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE, EDP_DYNAMIC_BACKLIGHT_ENABLE, EDP_REGIONAL_BACKLIGHT_ENABLE
                            00722h EDP_BACKLIGHT_BRIGHTNESS_MSB: 42011
                            00724h EDP_PWMGEN_BIT_COUNT: 10, ?0xc0
                            00725h EDP_PWMGEN_BIT_COUNT_CAP_MIN: 23, ?0x20
                            00726h EDP_PWMGEN_BIT_COUNT_CAP_MAX: 13, ?0x20
                            00727h EDP_BACKLIGHT_CONTROL_STATUS: 14
                            00728h EDP_BACKLIGHT_FREQ_SET: 43
                            00729h : fd // .
                            0072ah EDP_BACKLIGHT_FREQ_CAP_MIN_MSB: 12488908
                            0072dh EDP_BACKLIGHT_FREQ_CAP_MAX: 210
                            00730h : 6e de // n.
                            00732h EDP_DBC_MINIMUM_BRIGHTNESS_SET: 224
                            00733h EDP_DBC_MAXIMUM_BRIGHTNESS_SET: 194
                            00734h : 64 80 41 b6 16 ad 04 0b 1d d3 6f 05 // d.A.......o.
                        DPRX ESI (Event Status Indicator)
                            0200eh LANE_ALIGN_STATUS_UPDATED_ESI: LINK_STATUS_UPDATED
                        Extended Receiver Capability
                            02200h DP13_DPCD_REV: 1.4
                            02201h MAX_LINK_RATE: HBR2
                            02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED, ?0x20
                            02203h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
                            02204h NORP: 2
                            02205h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DVI or HDMI, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE
                            02206h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
                            02207h DOWN_STREAM_PORT_COUNT: 1, OUI_SUPPORT
                            02208h RECEIVE_PORT_0_CAP_0: ?0x28
                            02209h RECEIVE_PORT_0_BUFFER_SIZE: 256 bytes per lane
                            0220ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
                            0220ch I2C_SPEED_CAP: 10kbps, 100kbps
                            0220eh TRAINING_AUX_RD_INTERVAL: 16ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
                            02210h DPRX_FEATURE_ENUMERATION_LIST: VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
                        PCON HDMI CONFIG PPS Override Buffer
                            03000h CEC_TUNNELING_CAPABILITY: CEC_TUNNELING_CAPABLE, CEC_SNOOPING_CAPABLE, CEC_MULTIPLE_LA_CAPABLE
                            03030h : 01 00 00 00 00 00 // ......
                            03050h PROTOCOL_CONVERTER_CONTROL_0: HDMI_DVI_OUTPUT_CONFIG
                        HDCP 1.3 and HDCP 2.2
                            68000h AUX_HDCP_BKSV: b0 85 b5 d6 e2 // .....
                            68005h AUX_HDCP_RI_PRIME: 0f 34 // .4
                            68028h AUX_HDCP_BCAPS: BCAPS_HDCP_CAPABLE, BCAPS_REPEATER_PRESENT
                            6802ch AUX_HDCP_KSV_FIFO[0]: 00 00 00 00 fd // .....
                            68031h AUX_HDCP_KSV_FIFO[1]: 00 00 00 00 02 // .....
                            68036h AUX_HDCP_KSV_FIFO[2]: 03 e5 fd 00 00 // .....
                            680c0h AUX_HDCP_DBG: 10 00 00 00 00 00 b0 85 b5 d6 e2 00 00 00 00 00 // ................
                            680f0h : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0e // ................
                    }; // dpcd
                    message 0x01000: 10 02 cb 01 d5
                    lct=1 lcr=0 , rad= , broadcast=0 path=0 len=2 , somt=1 eomt=1 zero=0 seq=0 crc=0xb:ok ... ; crc=0xd5:ok
                    type=0x01:LINK_ADDRESS result:kIOReturnNotFound
                    LINK_ADDRESS dpErrWriteMsgDownReq result:kIOReturnNotFound
                }; // DisplayPort
 
Last edited:
Code: 
BRANCH_ID: 70 48 44 4d 49 66 // pHDMIf
Does that mean the adaptor in that amazon basic's cable is called "pHDMIf"?
 
toke lahti said:
I've got 3 "DisplayPort = {" 's.
The 3rd one is the only one with "BRANCH_OUI:" and it's from Apple.

1.
Code: 
DisplayPort = {
                    dpcd = {
                        Receiver Capability
                            00000h DPCD_REV: 1.4
                            00001h MAX_LINK_RATE: HBR2
                            00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                            00005h DOWNSTREAMPORT_PRESENT: PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                        Link Configuration
                            00100h LINK_BW_SET: HBR2
                            00101h LANE_COUNT_SET: 4, ENHANCED_FRAME_EN
                        Extended Receiver Capability
                            02200h DP13_DPCD_REV: 1.4
                            02201h MAX_LINK_RATE: HBR2
                            02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
                            02205h DOWNSTREAMPORT_PRESENT: PORT_TYPE = DisplayPort, DETAILED_CAP_INFO_AVAILABLE
                        PCON HDMI CONFIG PPS Override Buffer
                            03050h PROTOCOL_CONVERTER_CONTROL_0: HDMI_DVI_OUTPUT_CONFIG
                        HDCP 1.3 and HDCP 2.2
                            68000h AUX_HDCP_BKSV: 4b 9a 9b 51 2e // K..Q.
                            68028h AUX_HDCP_BCAPS: BCAPS_HDCP_CAPABLE
                        DP HDCP 2.2 Parameters
                            692c0h HDCP_2_2_REG_HPRIME: 2b 92 b4 1c 64 02 86 e2 89 f9 84 9d 69 7a 46 8a // +...d.......izF.
                            692e0h HDCP_2_2_REG_EKH_KM_RD: df 5d c1 10 76 ad 58 67 72 c2 04 18 71 66 59 06 // .]..v.Xgr...qfY.
                            69310h : a5 ba a2 2e 03 c6 bd 5b // .......[
                    }; // dpcd
                }; // DisplayPort
2.
Code: 
DisplayPort = {
                    (00000h: dpErrReadDpcd result:kIOReturnNotPermitted)
                }; // DisplayPort
3.
Code: 
DisplayPort = {
                    dpcd = {
                        Receiver Capability
                            00000h DPCD_REV: 1.4
                            00001h MAX_LINK_RATE: HBR2
                            00002h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED, ?0x20
                            00005h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DVI or HDMI, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE
                            00007h DOWN_STREAM_PORT_COUNT: 1, OUI_SUPPORT
                            00080h DOWNSTREAM_PORT_0: PORT_TYPE = HDMI, HPD aware, 600 MHz max TMDS clock, DS_MAX_BPC = 16bpc, PCON_MAX_FRL_BW = 0Gbps, FRAME_SEQ_TO_FRAME_PACK, YCBCR422_PASS_THROUGH, YCBCR420_PASS_THROUGH, YCBCR444_TO_422_CONV, YCBCR444_TO_420_CONV
                        Source Device-Specific
                            00300h SOURCE_OUI: 00-10-FA = Apple, Inc.
                            00303h SOURCE_ID: 41 41 50 4c 00 00 // AAPL..
                            00309h SOURCE_HW_REV: 0.1
                            0030ah SOURCE_SW_REV: 1.0
                        Branch Device-Specific
                            00500h BRANCH_OUI: 00-10-FA = Apple, Inc.
                            00503h BRANCH_ID: 70 48 44 4d 49 66 // pHDMIf
                            00509h BRANCH_HW_REV: 1.4
                            0050ah BRANCH_SW_REV: 2.25
                        Extended Receiver Capability
                            02200h DP13_DPCD_REV: 1.4
                            02201h MAX_LINK_RATE: HBR2
                            02202h MAX_LANE_COUNT: 4, ENHANCED_FRAME_CAP, TPS3_SUPPORTED, ?0x20
                            02205h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DVI or HDMI, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE
                            02207h DOWN_STREAM_PORT_COUNT: 1, OUI_SUPPORT
                        PCON HDMI CONFIG PPS Override Buffer
                            03000h CEC_TUNNELING_CAPABILITY: CEC_TUNNELING_CAPABLE, CEC_SNOOPING_CAPABLE, CEC_MULTIPLE_LA_CAPABLE
                            03050h PROTOCOL_CONVERTER_CONTROL_0: HDMI_DVI_OUTPUT_CONFIG
                    }; // dpcd
                    message 0x01000: 10 02 cb 01 d5
                    lct=1 lcr=0 , rad= , broadcast=0 path=0 len=2 , somt=1 eomt=1 zero=0 seq=0 crc=0xb:ok ... ; crc=0xd5:ok
                    type=0x01:LINK_ADDRESS result:kIOReturnNotFound
                    LINK_ADDRESS dpErrWriteMsgDownReq result:kIOReturnNotFound
                }; // DisplayPort
Click to expand...

The Mac mini 2018 has an integrated Intel iGPU that supports 3 displays.

#1 is for the adapter that is used to connect the Samsung display.

#2 has no display or adapter so there's no DisplayPort info to get.

#3 is for the adapter that is used for the HDMI port of the Mac mini 2018. There is no display connected to this but AllRez is able to get the DisplayPort DPCD info from the built-in adapter.

toke lahti said:
Code: 
BRANCH_ID: 70 48 44 4d 49 66 // pHDMIf
Does that mean the adaptor in that amazon basic's cable is called "pHDMIf"?
Click to expand...
That's #3. A manufacturer can put any info they like in the BRANCH_ID field. It can be ASCII or binary data. The OUI belongs to Apple, but I think Apple uses a chip from another manufacturer to do the DisplayPort to HDMI conversion. See the Mac mini 2018 teardown on iFixit.

This example:
Code: 
BRANCH_ID: 53 59 4e 41 71 00 // SYNAq.
Is for the Synaptics VMM7100


I don't see any identifying info for #1. Maybe there's a separate I2C address to get PCON (Protocol Converter) info?
I googled this:
"What info can be obtained using DDC or I2C from a DisplayPort to HDMI 2.1 Protocol converter?"
It mentions SCDC (Status and Control Data Channel)
The EDID obtained for your Samsung display says "SCDC Present". I think SCDC info comes from the display, not the adapter so it probably won't help identifying an adapter.
SCDC is described in the HDMI 2.0 spec.
 
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