Ok, this is a bit out there but it ties in nicely with what I do for a living so I thought it would be an interesting idea to float. How much is known about the folding algorithm? I work pretty heavily in FPGAs and have become fairly proficient at VHDL and Verilog coding. FPGAs have a lot of powerful resources available in them now and I have been working closely with Xilinx Virtex 4's which claim to have DSP resources (multipliers/adders) that run at 500 MHz. My thought is that it might be possible to implement part if not all of the algorithm in an FPGA and offload all of the processor work to another piece of hardware. If the algorithm does a lot of multiplication type operations it is possible that huge increases could be achieved with proper implementation of the algorithm. Of course I don't think anyone would be willing to buy the cards to run it on which typically run in the $5-$10k range, but there might be cheaper alternatives. Of course this would require time and motivation and I am severely short on time these days. I also doubt anyone would be willing to spend that much on folding so there is definitely a lack of motivation. Just though it was an interesting idea.