G5 Processor and Bus Slewing

[picnicbob]

Problem with speed tests in G5

Ok, seeing as the G5 doesnt have a level 3 cache, isnt it unfair to test the base model G5 against a base model G4? You have to take into consideration that the G5 uses RAM as it's level 3 cache unlike the G4 which already has a built in 2MB of cache to work with. Although 2MB really isnt that much, the G5 has 0. Shouldnt the tests be done with more ram in both computers (either top of the line both or something like 2GB in both) as to even out the difference in architecture? The tests run by Mac Addict at http://www.macaddict.com/news/news_007.html support this in the last test they did when the put 2GB of RAM into a G5 and ran photoshop tests. They should have put 2GB in the other models as well though. That would have been a true test.

 

[Phil Of Mac]

Since the G5 wins, L3 cache or not, I don't think it's that big of an issue.

You're testing an architecture with an L3 against one without an L3. That's an inherent unevenness. Just like testing an architecture with a G5 processor against one with a G4 processor.

 

[panphage]

Also, I think the consensus is that the L3 cache is added to G4s because their memory bus is too slow. The L3 is a kludge to improve performance since Moto can't improve the bus architecture. The G5's memory bus is megafast, so it doesn't need the L3 cache.

What is the speed of the bus between the G4 and its L3 cache anyway?

 

[MacBandit]

Originally posted by panphage
Also, I think the consensus is that the L3 cache is added to G4s because their memory bus is too slow. The L3 is a kludge to improve performance since Moto can't improve the bus architecture. The G5's memory bus is megafast, so it doesn't need the L3 cache.

What is the speed of the bus between the G4 and its L3 cache anyway?

The L3 cache on OEM G4 modules is accessed at 1/2 the speed of the CPU. The G5 accesses system ram at 1/2 the speed of the cpu. So overall the throughput potential for the two is the same though there has to be increased latency in accessing system ram rather than an on board L3 cache.