Surely sticking to 8P cores and just adding 2E cores each generation isn’t sustainable. Especially since many pro apps, like Logic Pro don’t even use the E cores.
I don't think it is two cores per generation.
M1 Pro/Max gimped 2 core E cluster ( half of the normal building block E-core cluster).
M2 Pro/Max undo the 'gimp' ... a normal 4 core E-core cluster.
M3 pretty it is just two E core clusters. So max out at 8 E cores. ( basically brining them into parity with two P core clusters ; 2*4 ).
[ And it is one of those hyper-symmetry things that seems to attract Apple's 'eye' often.
Same symmetry that is in the 'plain' M1/M2 . ]
M4 ...most likely ... better cores rather than more cores. Far more likely going to see NPU, AMX , GPU boosts in core counts or more specialized fixed function like image/video accelerators than more extremely general purpose cores. Some subset of workloads that were "high CPU core count" oriented 4-10 years ago will be pulled back into less generally useful logic that does that workload faster and at far lower power consumption levels. That is where the transistor budget will be skewed toward.
The major footprint of both the P-core cluster and the E-core cluster is the L2 cache. Toss in the AMX allocations for each and likely in the more than half the footprint range. TSMC N3 family through early N2 family probably aren't going to shrink L2 cache size at all. So can't increase core count without making die bigger. However, N3-N2 wafers are going to cost substantially more... so bigger dies means higher costs.
Throw on top Apple is fighting a major two-front 'war'. There are CPU core competitors in PC space ( Intel AMD). There are up-and-comers Qualcomm/Nuvia . And there are new GPU core competitors in PC ( AMD/Intel/Nvidia ) [ Intel stumbled hard out of the gate but if Adamantine works well
Intel Meteor Lake with L4 cache The patent confirms the use of “Adamantine” cache for Meteor Lake. Intel has already confirmed the use of Level 4 caches for its upcoming System on a Chip codenamed Meteor Lake. This was first reported by Phoronix in the recent Linux patches. Other than confirming...
videocardz.com
they may not lag far behind in iGPU zone for a long time. Probably not jump to winner, but just not way , way back.
Both AMD and Intel are trying to kill off dGPUs in most laptops. Not quite as radical stance as Apple's in killing of dGPUs in all laptops, but pretty close. ]
If Apple needs more than 8P/8E then should be looking for a far, far , far better chiplet design strategy rather than trying to pack them into a monolithic die.
The backside power and other gyrations that are going to be appied in 2025-2026 to start incremental progress on SRAM/cache shrinkage (density) increases are not likley to magically catch the back up to logic's density. It will be just less stuck and immobilized.
If the M3 Pro can get to 10P cores at least it gives some of us M1 Pro users a reason to upgrade.
Doubtful Apple added another P core cluster ( either half sized or full sized). 12 = 8 + 4 .
If Apple adds bigger AMX , bigger NPU , bigger GPU cores lots of M1 Pro users will still have reason to upgrade.
The way Apple organizes there cores in a 4 core cluster around as shared L2 cache is a dual edge sword. That means their clusters are coupled to the attributes of the L2 cache construction constraints about just as much as the individual cores. It is a shared resource. Less copying (between cores ) , but also more coupling in dependencies.
Similar with the 'abnormally large' giant L3 that all the cores share. Less copying but if L3 runs into construction constraints they all run into the same constraints.
Otherwise it’s likely to be another year on year decrease in sales isn’t it?
Extremely likely not. The year on year drop is because the Pandemic "buy everyone a laptop/PC with emergency money" bubble popped. If look at sales 2019 (or first half 2020 ) - 2023 there is no drop. ( just skip the bubble and look). The whole PC industry in in the mist of a bubble popping. This has exceeding little to do with the M1 vs M2 specifically.
If most of these 'boom" cycle systems get retired on a fixed schedule will likely see a mild boom/bust cycle down the road going forward. Again not much to do with the silicon and far more to do with customer standard refresh behavior.