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I'm not sure what to think about this G5 thing...

Re: A possible way...

Originally posted by Catfish_Man
A 64 bit chip would.... work like Altivec and accept 2 32 bit words at a time. It would require programs to be written to take advantage of it, but it would basically be like a mini-Altivec for non vector operations. If the program didn't have the type of operations that use SIMD then it would give any improvement.
Click to expand...

That's exactly my guess. If you can ***ign sub units by speed to reduce power, there's no reason NOT to use it for splitting the data path.

Effectively IBM has built a 2 core, bridgeable, on-the-fly throttleable paired 32 bit G3 at half the power consumption of G4 and a 256 bit wide L1 cache that can also be ***igned in chunks on the fly.

(pant, pant......What a mouthful!)

Indications are that G5 is more multi-processor friendly, so 4 two-on-one-chip, Ghz, bridgeable G3's. That's SICK. Stick that on a 200Mhz bus with 4 Gigs and Itanium looks like a toy.
 
The Spec for the 750FX (G5)

Shows a 200Mhz bus and design tolerance for up to 20 times the bus speed:

Once the Heat issues level out with the basic circuit tolerances we'll see 4Ghz G5's at 200Mhz bus 64 bits wide, splittable.

This is a thermonuclear hand grenade for the desktop.:D

" I spit on your puny, girlie P4."

" I'll soak your 10 D6 mace and hit you with my 10 D20 walking stick.......When the Character description says {GOD} in the Species slot, don't pick a fight.":D :rolleyes: :cool:
 
The 750fx...

...is NOT the G5. It's a G3. A new, spiffy G3, but still a G3. No SMP. No Altivec. PPC 750 series core. The G5 is a Motorola project. With Altivec. With SMP. 8500 series core. The 750fx (Sahara) is awesome, but the G5 will crush it. Badly.
 
Aaaaaaahhhhhhh........I See.

So the links to Sahara labelled as G5 were misleading. Do you have a link to G5?

If that's just Sahara......EEK!!

Sahara is ugly enough to make Apollo look kinda skimpy. Perhaps we will see Sahara in iBooks, Apollo in iMac and TiBook and G5 in Towers by the end of the Year.
 
out of hand

guys, you're getting alittle caught up in rumors. there will be no 4 ghz g5. yes the new g5 has a 200 mhz bus, see the p4 actually runs two buses, each being 200mhz and for sales reasons they market it as a 400mhz bus, very misleading since the two buses screw themselves and rarely work together making a bottleneck. this is why apple choose to stay with one fully sped bus that works correctly. however, seeing how the main core will be an amd, that's right an amd design, apple has licensed the quadspeed architecture from amd as has cryrix and other board manufacturers. with this in mind and the fact the ddr ram chipset is a via take off and generally runs along the bus of an amd 266 bus better, they may improve intel's 200 mhz bus to match the ddr 2100 which runs at 266mhz. 64 bit will allow for over 2 gigs of ram and applications to take more advantage BUT as with the altivec engine, it needs to be optimized for that, you wouldn't believe how few programs are actually 64 bit, most are still 32, so it barely matters. the g5 will not, please note this people, it will not surpase whatever speed mark intel wants to come out with, they already have a 3.5 ghz chip, except for the fact it needs a mini ac to run, but if they even hear a rumor of something faster, trust me they will release a faster chip, they don't release till they need to. it doesn't mean they are faster, it just means the sheep of pc buyers will look and say oh bigger number, must be faster. the new g5 will do the same thing the g4 did, it will improve, it will be faster, better, all of those nice things, but it will not destroy boundries, marketing plays a roll here people, why jump out with something you can't follow up to, you send out you're fastest thing and the next week people are looking for more. try to think of this in video game terms, nintendo 8 bit, then 16, then genesis matched it, then they went 32 and other companies did and they all went along and then 64 and then so on, so look at it this way, nintendo, xbox, ps2, = apple, amd, intel, it runs like a scheduale and there are reasons why, would you buy a super nintendo if the ps2 was out at the same price? so why jump to a 4 ghz when all you have to match is 2 and when your customers don't expect you to jump so far, they expect ghz range, to mid 1.5 to 1.6, that will sell, then they can continue from there. be realistic about things. i'm sick of the people who go nuts and overboard and really think they know what they are talking about just by reading rumors. know the business side behind everything, it plays a bigger part than you think, and check other companies that have good ideas, because even though apple doesn't talk about alot of the places they get hardware and software ideas, the companies they get them from love to play it for all it's worth.
 
one last thing, just because you have the technology doesn't mean you will use it right away, timing is key and during a down time, surprises come in handy. and just becuase ibm or others talk about chips, doesn't mean that others get to use them or that they are even ready, if you check ibm things like a flat crt came up, that's right, two guys made a flat crt that is 2 inches thick and much much cheaper than flat panels, and, can be made in much bigger sizes, but you don't see it on best buy's shelf yet do ya. that was months ago too. so, my point here is, think what is smart for apple, not what you dream about. motoroloa could have 5 ghz chip it wouldn't matter, you make more money by going in stages and using timing to your advantage.
 
You just blew my mind man.... :(
help... just how many differnect processors is the mac going to have at one time? 4? 5? more???
Wow we all now know why apple processor are slower in clock spped right?
That all made sense to all of you who have college degrees in engieering right???
:eek:
 
That comment about P4s having 2, 200Mhz busses is not ENTIRELY accurate from the reading that I have. The P4 actually has a pipeline stage, the Arithmetic-Logic Unit operations (simple integer and logical ops) that can effectively run at double the bus speed (400 Mhz). Everyone should go to arstechnica.com because you can find the best database on the structure of the P4, the G4e, the K7 (AMD duron), and other processors.

I must admit that the P4 has some very revolutionary techniques, but sadly Intel kills the chip by using the narrow and deep approach to the processor. I love the idea of decoding instructions and predicting the branches before putting them onto the L1 cache. This actually reduces the number of pipeline stages, but when the level 2 cache is drawn from, it adds another 8 stages to decode and predict (which is understandable although excessive). I did my own calculations and in theory, the P4 running at 2.2ghz gets information off of chip about the same speed as the G4e running at 867Mhz (when you divide the 867 by the 2200 (for comparitive speed) and multiply that by the number of stages (20 in the normal cases of the P4)). The P4 goes about as fast as an equivilent 7.2-7.5 stage G4e. Now this would be in theory, but there are many other factors that speed the P42.2Ghz past the G4e867Mhz.
 
Internal pipeline stage related to BUS frequency??

Originally posted by KingArthur
The P4 actually has a pipeline stage, the Arithmetic-Logic Unit operations (simple integer and logical ops) that can effectively run at double the bus speed (400 Mhz).
Click to expand...

The ALU pipeline stage(s) you refer to run(s) at twice the frequency of the CORE, not the BUS. There is a HUGE difference here. The bus and the core are pretty much completely decoupled in modern microprocessors outside of frequency ratios.

I believe I've heard the P4's data bus is double-pumped. This is probably what people are referring to.
 
Re: What is it...

Originally posted by Catfish_Man
...about Intel's Itanium that gives it such high performance? I know it's 64 bit, but as the posts above say, there's no reason why that should make a large performance increase.
Click to expand...

The architecture of the IPF (Itanium Product Family) is completely different from other superscalar RISC processors. It is generally referred to as VLIW (Very Long Instruction Word) or EPIC (Explicitly Parallel Instruction Computer.)

Instead of having several execution units hidden behind some layer of out-of-order issue circuitry, IPF instead lays the processors execution pipelines out for more direct access by the software writers. IPF handles bundles of up to three instructions at a time. In theory, this could enable up to 3x the intruction throughput of other current microprocessors that only retire one instruction per cycle. (In reality, NOPs and instructions that are predicated out of existence reduce this number.)

The downside? Compilers get extremely messy because now THEY get to deal with the complexity of managing the hardware that used to be handled by the hardware itself. IPF is still heavily in the early stages of development for these sorts of compilers. It remains to be seen if the gamble of the new architectural approach pays off.

Oh did I mention that these are presently incredibly power hungry (as most new architectural implementations are)? I'd expect the IPF to stay in the high-end workstation and server space for awhile.
 
Re: 200MHz???? HA! 400MHz baby!

Originally posted by -=AsukA=-
whats all this talk of 200 MHz system bus speed? the G5 is definetly 400MHz Bus speed! yeas were talking about Mac MHz (up to 2 times faster that PEE CEE MHZ) so that mean the Pentium 4s day in the sun is numbered!

dont believe me? look for your self: http://www.theregister.co.uk/content/39/21692.html
Click to expand...

That's the same Register article that's been widely discredited. If you look at the date of publication, it was put out in September, more than four months ago, and that's assuming it actually had something to it to begin with, which it apparently didn't.
 
Another Byte out of logic

I meant to say that the ALU is double-pumped, but accidently wrote the wrong info. But the ALU did get a lot of hype, and that is what I think this 400Mhz P4 bus thing comes from. The one funny thing about this ALU is that it is not well-fed; therefore it frequently wreaks havok with bubbles. Branch mispredicts kill it. The information that I have been reading-up on has provided me with a greater knowledge of how these processors actually work.
Quite facinating.
 
P4 buses and uses for 64 bits.

Howdy -

Some information on the P4/P4 Xeon/P4 Xeon MP bus- It is a split transaction (pipelined, packet based) bus. The _data_ rate _is_ 400Mhz. Data is transferred on the data bus in 8 byte chunks (8 8 byte chunks give you a 64 byte cache line), so if the data bus is fully utilized and you have a 100 Mhz front side bus (data bus is quad pumped), you can approach 3.2 GB/sec. Many of the bus strobes (control signals) run at 100 Mhz. One drawback to the shared FSB approach to SMP is that all the processors on this bus share the same bandwidth. One positive to this approach is that it is very easy for other processors on the bus to "snoop" on transactions by other processors making the cache coherency protocol a little easier to implement. So if you are trying to implement a memory controller/northbridge or whatever you want to call it, you want to make sure that you can support the kind of bandwidth that the processor can demand. In a server type system this usually means multiple DRAM channels and very wide data paths in the memory controller. Otherwise you run the risk of starving the processor for data which obviously has performance implications.

As far as 64 bit processors go there are several benefits. One that was mentioned here is being able to address more memory and/or increase the amount of virtual memory that you can address. I.e. 64 bit pointer types. The main use of these (besides more precision for number maths) is for sparse databases. If you want to maintain a large database or do data mining or scientific applications you may need/want this capability. The average home user is usually not going to need this kind of precision or capability for running their spreadsheets or surfing the web, but if you are into scientific applications or are planning on running a big database, they are nice.

Hope this is informative,
Swatara

"What can change the nature of a man? Regret..."
 
You are right except for one technical error you made. MHz is not data rate. That's bandwidth. MHz is a measure of the frequency. That is ALL MHz is a measure of. Hz is the SI unit for cycles per second. Therefore, it is a 100MHz system bus that is quad-pumped that has the bandwidth of a 400MHz bus. But that doesn't make the frequency of the bus higher. It makes it transfer data at the same speed overall as a 400MHz bus that is single pumped, but it does not make the 100MHz quad pumped bus a 400MHz bus.

Bandwidth is the data transfer rate. MHz is the frequency rate. Having a bandwidth equal to that of a higher-frequency bus does not make your bus have that higher frequency.
 
Hello-

I made no technical error.

Bandwidth is the amount of data that is transferred in one cycle.

Bandwidth = frequency * width of bus in bytes. I.e. a 100 Mhz bus that is 8 bits(1 byte) wide could have a theoretical peak bandwidth of 800 MB/sec. So a 400 Mhz bus 8 bytes wide has a theoretical bandwidth of 3.2GB/sec if the bus protocol and memory controller are good enough to keep the bus busy.

How do you think that data is sent on that bus? It has to be clocked, its just not asyncronous between the two devices. In this case it is a source syncronous design where the memory controller or the processor drives two, 200Mhz clocks that are 90 degrees out of phase. What it boils down to is that the data is clocked on both edges of a 200Mhz clock - sort of like DDR Dram. The data bus _IS_ 400Mhz. I should know, I have the Intel P4/P4 Xeon/P4Xeon MP orange documents sitting right in front of me. :) These are not new design techniques..

BTW, I'm not posting these because I am a Mac hater or POWER/PowerPC hater (I am a Computer Architect/ASIC Designer for IBM)... I just have happened to work on memory controller designs for both Power4, IA-32 Foster, and the follow on to the IA-64 Merced(now known as Itanium). Believe me, it would be great to see Macs use GP(Power4).

Regards,
Swatara
 
SDRAM itself is asyncronous. So, to make it so the processor and the RAM can talk, they sink it to a bus clock cycle.

The "400MHz" claim is because of two 100MHz bus operating in the same way of DDR SDRAM. DDR sends two packs of data per clock cycle, on one the up, and on the down.

That doesn't make the clock frequency any higher. It means you can transmit twice as much data at the same frequency as before.

Bandwidth on a SINGLE pumped system is "Bandwidth = frequency * width of bus in bytes". However, on a double pumped bus you have to multiply it by two, because it can send TWICE as much data at the same frequency.

But the FREQUENCY, the clock tick, is THE SAME. I would hope, since you are a system architect, that you would know this. Browse over to arstechnica for some more in-depth explainations.
 
"The _data_ rate _is_ 400Mhz"

If you mean that the data rate is equal to that of what you can transmit on a 400MHz bus, you're right.

But, if you mean that the actual data rate is 400MHz, you're wrong.

400MHz isn't a data rate. 400MHz means the clock cycles 400 million times per second. But even Intel admits that it's a 100MHz bus.

3.2GB/s is the data rate. The quad-pumped (I know it's two buses, but Intel intends for them to act as one, so I will use their explaination) 100MHz bus has the same DATA THROUGHPUT as a 400MHz bus... but it's a 100MHz bus.

When I say that the bus is 100MHz, I mean the clock cycle. The frequency. But DDR and RDRAM allow us to double what you can do with the frequency. So the bandwidth is equal to that of a doubled frequency. But that doesn't make the frequency itself equal to that of the higher frequency.
 
"What it boils down to is that the data is clocked on both edges of a 200Mhz clock - sort of like DDR Dram"

I think I see our misunderstanding:

We both agree that the data that can be transmitted is equal to that of the higher frequency.

But what we disagree on is calling it 400MHz. Yes, the data gets transmitted at the same rate as it would on a 400MHz clock cycle, but it's on a 100MHz clock cycle. (I think I just don't like fudging things. To say it's a 400MHz bus implies that you could then double pump it to get the equal data transfer rate of a 800MHz bus.)

Part of the problem that I think is confusing everybody (not you, I mean people in general) is that electricity goes no faster in a 66MHz or a 133MHz bus setup. The electricity takes just as long to reach point B from point A. It's just with a higher frequency you can have more peaks per second, so you can transmit more data each second, so you can transmit files faster because it doesn't have to wait as many seconds for enough peaks (and width double-pumped buses, it can send twice as much data on the same clock).

Anyway. I hope nobody's upset about my amount of posts, I was just trying to make my point clear. (If anyone is curious what I'm trying to say, browse over to a page on my site http://jeni-lee.com/anshelm/rants/fsb.html. Note: requires Flash 5 plugin)
 
Those rumors you're hearing about IBM and the G5 without AltiVec... can you guys be mistaking these with the IBM Power5?
 
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