Improvements of Skylake

Discussion in 'MacBook' started by izzyfanto, Apr 25, 2016.

  1. izzyfanto macrumors regular


    Nov 22, 2011
    Interesting, very lengthy AnandTech article last year on Skylake. Pulled some points of interest for those who want to know the actual details that make 6th gen better. Very technical reading, but fun IMO. Hope it's of help.
    1. "Prior to Haswell, voltage regulation was performed by the motherboard and the right voltages were then put into the processor. This was deemed inefficient for power consumption, and for the Haswell/Broadwell processors Intel decided to create a fully integrated voltage regulator (FIVR) in order to reduce motherboard cost and reduce power consumption. This had an unintended side-effect – while it was more efficient (good for mobile platforms), it also acted as a source of heat generation inside the CPU with high frequencies. As a result, overclocking was limited by temperatures and the quality of the FIVR led to a large variation in results....For Skylake, the voltage regulation is moved back into the hands of the motherboard manufacturers. This should allow for cooler processors depending on how the silicon works, but it will result in slightly more expensive motherboards."
    2. "...the level of control and power gating that has been incorporated into the processor, allowing the hardware to either disable completely, move into the most efficient power mode, or even duty cycle to reduce power. A big part of this is under the term ‘Intel Speed Shift’, Intel’s new methodology of allowing quick frequency changes and responding to power loads....The PCU is essentially a microcontroller (we’ve seen references to a full Intel architecture (IA) core in there) that monitors and computes the power requests and consumption portfolio of the separate silicon areas, providing information that can allow parts of the CPU to be power gated, duty cycled, or adjust in frequency and voltage. We’ve mentioned in our initial Skylake review that going into the CPU itself are four power rails (more with eDRAM). This is an adjustment over Haswell/Broadwell which only had one power rail due to the integrated voltage regulator, which is now moved back on to the motherboard for a combination of reasons related to complexity, efficiency, die area and heat generation...Being able to react due to power demand and efficiency requirements is a key aspect of Skylake here."
    3. "...faster response vehicle to frequency requests and race to sleep by migrating the control from the operating system back down to the hardware. Based on the presentations, current implementation on P-states can take up to 30 milliseconds to adjust, whereas if they are managed by the processor, it can be reduced to ~1 millisecond....which also allows for quicker changes when necessary to respond to interactions with the system to keep responsiveness high but power consumption low....What Speed Shift entails is that ultimately the OS has the highest level of control unless thermal states kick in. The OS can define either the whole of the frequency range (from LFM to P0) or a certain part of that range and hand control back to the processor. This then becomes an ‘autonomous P-state’, allowing the adjustment of frequency to respond on a millisecond timescale. At any time the OS can demand control of the states back from the hardware if specific performance is needed."
    4. "The high range algorithm is of most interest – clearly moving to higher performance affords better response times and quicker time-to-completion, albeit at the expense of energy efficiency. It can be difficult to ascertain whether a user wants something done quickly, or something done efficiency...Intel’s algorithm also performs an analysis of the workload, whether it is sustained, variable, bursty or can be moved to fixed function hardware, but at any time the OS can jump in and either adjust the algorithm characteristics or take control altogether."
    5. "Running Cinebench at a steady state performance profile will get zero benefit. Intel is aiming specifically at rapidly changing frequency scenarios here...standard benchmark profiles that speed through user entry significantly faster than a normal user would not see any benefit from Speed Shift"
    6. "However as Intel seeks to further optimize their power consumption, they have been running headlong into the laws of physics. The voltage/frequency curve is just that, a curve, meaning that it flattens out towards the bottom. As it turns out it flattens out more rapidly than you’d think due to the existence of a threshold voltage for transistors, which is the minimum voltage required for a transistor to operate. As a result of this effect, idling at even lower frequencies sees rapidly diminishing returns once you drop below the threshold voltage, and at this point reducing frequencies is no longer an effective way to reduce power consumption....In Broadwell, Intel introduced the idea of Duty Cycle Control (DCC) to solve the idle power savings problem for the processor’s iGPU. A solution that is both a bit brute force and a bit genius, with DCC Intel outright shut off the iGPU for a period of time...Catching up to Skylake then, Intel has taken the duty cycle concept to the next stage and implemented DCC on the CPU cores as well. Similar to Broadwell’s iGPU implementation, this involves rapidly turning the CPU cores off and on to achieve further power savings beyond what idling alone can offer. In the case of Skylake this process can occur as often as every 800 microseconds.
    7. "Of all of the power saving features introduced in Skylake, duty cycling the CPU cores is likely to be among the most potent of these features."
    8. SUMMARY: "Skylake is a mobile first design, and Intel has focused a lot of resources in two areas. First is power delivery, by adding more power gating and finer frequency control direct to the hardware through Speed Shift, the processor can take advantage of unused parts as well as improving the power consumption of a non-steady state workload. Speed Shift does two things - it requires operating system support, but it allows the operating system to hand control of frequency adjustments back to the hardware within an OS specified range. As the processor is able to adjust its own frequency settings almost 30x faster than the operating system, it can respond to dynamic workloads such as those experienced in day-to-day use of a device faster than the OS. The second part of Speed Shift relates to the power states of a system, and the Skylake platform allows this hardware control to be substantially more granular than the high level P-states, allowing the onboard controller to determine the best efficiency mode to run the processor with respect to system power (which is also now tracked). When the system is in its most efficient state and performance is not a concern, Skylake can also induce a duty cycle for the processor cores, switching them on and off, to remain at the most efficient power state when performance is not a priority."
    The main things I took away from this is that Skylake is a M focused design, and as such the improvements are not going to be noticed as much in benchmark scores testing raw speed for a limited time, but more in everyday usage, as the M chips have been enhanced for bursty performance. Intel's algorithms, TDP, DCC, power efficiency through voltage regulating, and CPU sleep (response speeds of 1 milliseconds instead of 30) and overall greater CPU management versus OS management.
  2. where is it macrumors 6502

    where is it

    Jun 19, 2012
    Well that was the most fun I've had in years.
  3. izzyfanto thread starter macrumors regular


    Nov 22, 2011
    Haha! It was interesting at least, no?
  4. KPOM macrumors G5

    Oct 23, 2010
    A lot of this relies on the OS. Windows 10 is written to take advantage of Speed Shift. Hopefully part of the reason Apple waited so long after Broadwell and Skylake to release the MacBooks over the last 2 years has been to optimize OS X for the power management features Intel has developed.
  5. izzyfanto thread starter macrumors regular


    Nov 22, 2011

    It does seem that Intel provided a fair amount of CPU control for low P states.
    "faster response vehicle to frequency requests and race to sleep by migrating the control from the operating system back down to the hardware. Based on the presentations, current implementation on P-states can take up to 30 milliseconds to adjust, whereas if they are managed by the processor, it can be reduced to ~1 millisecond'

    Do you think the Duty Cycling is dictated by the CPU or the OS?

    It also seems the performance algorithms are built into the CPU, no? Or are they just built into the CPU but then utilized by the OS? I'm not an engineer so I'm just trying to use dummy logical thought.
  6. deeddawg macrumors 604

    Jun 14, 2010
    Interesting yes.

    Fun? We apparently have different ideas of what that means... :)
  7. izzyfanto thread starter macrumors regular


    Nov 22, 2011
    Yeah, I guess fun is the wrong word. lol. I just find trying to figure out complex things that I use on a daily basis makes me more appreciative when I notice those complex things doing their job when I need them too.

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