The reports I've heard indicate that the restriction was due to PCIe lanes on the CPU itself. Each pair of ports is run from a single Thunderbolt controller. The left side has a full x4 PCIe link for the controller, while the right side has a x2 link (basically equivalent to Thunderbolt 2 in bandwidth).
What I've been trying to figure out is what the exact restriction is. I think it's a limitation of lane configurations that Intel has made available. The dual core chips have 12 lanes, which should be enough, but from the best I can parse their documentation, they only make a single x4 link available in any configuration. By comparison, the quad cores in the 15" have 16 lanes, which use x8 for the GPU, and then 2x4 for the Thunderbolt controllers.