Please everyone do your search before... The Nehalem Xeon got the same QPI/memory architecture than Core i7 right ? So ...
QPI:
From a technical point of view, a QPI link is bidirectional and has two 20-bit linksone in each directionof which 16 are reserved for data; the four others are used for error detection codes or protocol functions. This works out to a maximum of 6.4 GT/s (billion transfers per second), or a usable bandwidth of 12.8 GB/s, both read and write.
FSB:
The FSB on the most recent Intel processors operates at a maximum clock frequency of 400 MHz, and address transfers need two clock cycles (200 MT/s) whereas data transfers operate in QDR mode, with a bandwidth of 1.6 GT/s. With its 64-bit width, the FSB also has a total bandwidth of 12.8 GB/s, but its usable for writing or reading.
So a QPI link has a theoretical bandwidth thats up to twice as high, provided reads and writes are well balanced. In a theoretical case consisting of reads only or writes only, the bandwidth would be identical to that of the FSB. However, you have to keep in mind that the FSB was used both for memory access and for all transfers of data to peripherals or between processors. With Nehalem, a QPI link will be exclusively dedicated to transfers of data to peripherals, with memory transfers handled by the integrated controller and inter-CPU communications in multi-socket configurations by another QPI link.
The advantage of an integrated memory controller isnt just a matter of bandwidth. It also substantially lowers memory access latency.
More here.
Thanks for clearing that up between the hardware differences. I just didnt have the technical stand point to compare each hardware side by side as you have.
Finally a reasonable voice.