M3 Chip Generation - Discussion Megathread

[deconstruct60]

Your math is odd... (as JouniS said but I was writing this while their comment appeared)

Assuming an e-core = 1/4 of a p-core:

Let P = the performance of an M2 P-core

M2 Pro = 8P + 4 * 1/4P = 9P
M3 Pro = 6 * 1.15P + 1.3 * 6 * 1/4P = 6.9P + 1.95P = 8.85P

if the P improved by 15 and the E improved by 30% then the E is likely not still 1/4P. There is a bigger jump in the E so it pretty likely climbed to a higher fraction of a P.

100 ( 1.15) ---> 115
25 ( 1.3 ) ---> 32.5 32.5 / 115 --> 28% ( not 25%).

6.9 + 2.18 P = 9.08P

The ratio of E/P isn't staying constant. The E cores are progressing faster when better matched to a denser fab process and/or more optimized libraries ( on internode upgrades) . Also have less problems with SRAM/Cache not shrinking because use relatively less cache ( so a higher percentage of the cluster can get a better bang-for-the-buck increase).

 

[senttoschool]

This could explain why Apple reduced the memory bandwidth. So maybe we shouldn't expect worse perfromance.

Chips and Cheese

Apple’s recently announced M3 Pro carries forward M2 Pro’s design goals, but memory bandwidth has been reduced to 150 GB/s. The M3 Pro can be configured with 18 GB or 36 GB of DRAM, compared to 16 or 32 GB on the M2 Pro. That divisible-by-3 number suggests Apple has switched to a 192-bit memory bus. In the discrete GPU world, the RX 6500 XT has just under 150 GB/s of bandwidth and slightly less FP32 throughput than the M2 Pro’s iGPU. M2 Pro’s very high DRAM bandwidth likely wasn’t helping most applications. A narrower, better utilized DRAM bus could save packaging and power costs.

Like Van Gogh and console chips, M2 Pro’s large memory bus aims to feed the GPU. Achieving the same 200 GB/s figure from the CPU side is not possible, but the CPU still benefits from it. 125 GB/s is a lot of bandwidth for eight cores, and is out of reach for desktop platforms.

LLMs easily saturate the bandwidth.

 

[altaic]

I think you are underestimating the performance of the e-cores. I remember reading something before the M1 Macs came out (after the processor was announced) that e-cores fully pushed to it's limit was around 70% as performant as the performance cores... I calculated a guess at what the multicore geekbench benchmark would be for that computer based on everything that was out at the time and using that 70%.... and that geekbench benchmark was actually very close. I highly doubt the e-core is only 1/4 of a p-core. Also you have to factor in the fact that one p-core operating is going to perform at 100%, but when you get up to many p-cores they are not going to run as it was a single core... at a certain point those performance differences between more e-cores and p-cores will narrow in performance, while the e-core will still be just as efficient as it was for the first one. The equation is much more complicated, which is why you hear Apple having multiple different versions fabbed and tested before deciding.

For sure, I was making a conservative argument (though 70% sounds quite high to me). As I just replied in a different post, I avoided assuming scaling characteristics because peoples' grievances were not about a specific task.

 

[Mathew31de]

Good Morning,
interesting insights so far, but a little bit silicon centered 😉

With the M3 and the M3 Max ‚lite‘ we now have 4 different speed/power categories, much like intels i3/5/7/9 but a lot more useful.

Whats missing here is the actual max frequency, they are allowed to perform. Apple furthermore talked about a new and better cooling system, which is especially needed for the new max chips or to compensate for different core counts with higher frequencies.

Maybe we will for the first time see higher clocked M3‘s and M3 Pros in contrast to the M3 Max ‚lite‘ which is clearly a binning product to mitigate possibly higher defective M3 Max numbers and the M3 Max .

 

[bkkcanuck8]

For sure, I was making a conservative argument (though 70% sounds quite high to me). As I just replied in a different post, I avoided assuming scaling characteristics because peoples' grievances were not about a specific task.

It sounded high to me at the time but the math using it was close enough to what the processor actually produced as an all-chip performance - I don't think it is far off... after all an e-core will optimize efficiency over performance -- but it still has to handle substantial performance for normal everyday tasks to be worthwhile in a laptop use - otherwise it would be mostly idle and useless.

 

[Boil]

@sv8 wondered about the Ultra (and possible quad-chip M3) being on N3E. Their reasoning was incorrect, but I noticed something just a little while ago that bears on that.

Looking at the Max's die shot, where is UltraFusion?? Did they just hide it (IIRC they did in some of the early pictures of the M1 Max)? If so it would have to be at the bottom, under the GPUs and SLC/RAM controllers, which is reasonable.

But what if there's another explanation?

They've already changed their pattern (if two generations makes a pattern) - the Pro and Max are clearly quite different from each other, not sharing nearly as much of their design as previous generations. Perhaps the chip that will be the basis of the Ultra is NOT the Max, this generation. Maybe there's no Ultrafusion connector in the M3 Max die shot because it doesn't exist.

This would be pretty surprising - I wouldn't expect them to do a whole new floorplan for chips making up an Ultra, as it would seem to be way too low volume for that. But... They obviously know a lot more than I do, maybe they see a good reason to do this. Maybe they count it as another learning step towards a future full of high-density chiplet interconnects, and therefore worthwhile just for that.

Maybe they need to do more work because they want it to go 4-way as well as 2-way?

Anyway, N3E vs. N3B is a sideshow for this, but: If they have to design M3-class CPU, GPU, and NPU cores for N3E anyway (for the A18, and maybe an M3+?), AND they have to do a separate design for M3 Ultra+ chips, maybe the added cost of redoing the entire M3 Ultra chip on N3E doesn't seem so crazy to them.

If this entire chain of speculation is correct, then we could see N3E M3 Ultras in 2024. Otherwise, it's a near certainty that we'll see M3 Ultras on N3B.

This earlier post makes some points that seem to align with the possibility of the M3 Max SoC being produced with varying features/capacities...?

Something to do with mask sets and steppings, I dunno, I am no engineer or anything, just a dude who is interested in high-end ASi machines...

Just to tweak @deconstruct60, WWDC 2025 will give us a M4 Extreme Mac Pro Cube using the N3X process, the ultimate macOS personal workstation...! ;^p

 

[iPadified]

I, for one, am on your side.
There's way too much noise being generated by people based on god-knows what, but certainly not any technical competence.

Don’t pat yourself too much on your shoulder. You and some others are speculating just as much about the the M3 architecture although with deeper technical knowledge. As far as I see, there is no solid scientific evidence presented but a try to reverse engineer and explain Apple chips. As long as you do not present the blue print of the SoC design, you are without evidence. The photos of the chip layouts cannot tell much about the core architecture but maybe number of the different blocks.

As a generalist forum, other are interested in other endpoint points such as total performance increase which includes marketing and product segmentation. They should be free to do so without being looked down upon.

 

[Pet3rK]

I'm not taking a side on the whole argument you're having, but it's pretty funny you saying he has no idea what he's talking about when you entirely botched your claim that the M3 Pro SoC doesn't have TB4 and can't attach multiple external displays. (Pro tip: It does and it can.)

Yup. But I'm going to give him the benefit of the doubt though he soured me a little bit.

 

[Confused-User]

[...]Also you have to factor in the fact that one p-core operating is going to perform at 100%, but when you get up to many p-cores they are not going to run as it was a single core... at a certain point those performance differences between more e-cores and p-cores will narrow in performance, while the e-core will still be just as efficient as it was for the first one. The equation is much more complicated, which is why you hear Apple having multiple different versions fabbed and tested before deciding.

This is an interesting but flawed argument.

To make it a little more concrete, I believe that you're saying that when mixing slower and faster cores in a "normal non-embarrassingly-parallel task", each will sometimes have to wait for work product from the others, and in that circumstance the slow cores will be able to use what would be "wait time" on P cores to finish up their subtask of the moment, thus hiding that slowness in what would otherwise have been wasted cycles.

That's true. But there is a downside that, depending on the specific workload, may (or may not) completely claw back any such gains: Sometimes it will be a P core doing the waiting, not an E core, and if it's waiting for an E core to finish instead of another P core, that wait (and thus wasted cycles) will be all that much longer.

 

[Pet3rK]

there have been many, 10,20,30x comprehensive reviews on YouTube where people run exhaustive tasks to try and get the m1 and m2 chips to throttle under load. we are talking about people running 10 YouTube videos simultaneously while scrolling through 4x 40MP images in adobe. the gist being: it is near impossible for a normal user to be able to discern the difference between m1 and m2. you are far more likely to be vram and ram bound.

That's not a normal user if you have 4 x 40MP photographs. You are now going into professional territory. On the UI stuff, sure, it's hard to notice especially on browsing but when you include going through 40MP pic then it's a different story.

And there's a lack of benchmarks and tests on here. Someone did a MatLab test but it's done on unoptimized software(R2023 is recently released relative to their review which they didn't use) but that's a small subset since there are other software to use. If you watched the keynote, they showed an Astronomer using glue. I don't know if they can do it but using terabytes of radio telescope data would be a rather good way to measure performance on extreme ends. Also using TetrUSS or FUN3D for a more let's say interesting test.

 

[Confused-User]

I think these chips are not performing as expected and Apple went into damage control trying to figure out what to cut to reduce thermal throttling. The GPU is a huge upgrade and that is going to add a lot of heat and battery draw. The 3nm process is not as efficient as they thought.
[...]
Sometimes a new process or denser process can be better and sometimes it has issues. I think Apple has issues with TSMC first gen 3nm. But this all just a big guess on my part.

It can be useful to speculate about some things, given insufficient data. But what you're doing here is speculating about something for which we already have a bunch of data. You're just wrong. There is no significant issue. The process is pretty much where TSMC said it would be. This has been exhaustively covered already here and in the thread @leman started about N3.

I agree the e cores are more powerful than people think. That being said if Apple was going to cut the P cores they should have added an additional two e cores for a 14 core setup. Then we would have had better multi core performance and better battery life as things that can be done using more e cores than using the P cores would save battery with no drop in performance. I think Apple hit a thermal envelope wall with the new GPU and they couldn't add more cores or too many P cores due to thermal constraints due to the new 3nm process on TSMC.

You don't know that 2 more E cores would result in better battery life. Work distribution is a complex task. It may be that for any task not close to saturating all the cores, 2 more E cores would be of no use. You know who does have a much better idea of whether that's true or not? Apple.

The argument about a thermal wall for the Pro is pretty ridiculous. They're getting a Max into the 14" chassis. The Pro is not a problem.

 

[Confused-User]

Thank you, confused-user-san !

I couldn't explain it because English was difficult for me, but you spoken for all my guesses for me.

I have a feeling that the N3E will made to the A18 and a cheaper version of the M3 (e.g. M3E) for the MacBook Air.

So I thought there might be a possibility of designing Ultra/Extreme with N3E as well.

You're welcome. My first reaction to this was, again, that's ridiculous. And honestly I don't think you're right- I think we'll see the Airs + Mini soon, either in November or in January, on N3B.

But it's not really ridiculous. Assuming, as is likely, that they will reimplement the M3/A17P cores in N3E, then... if they're willing to wait for N3E for the Airs and Mini, that could well happen.

The reason I still don't think this is correct is that I think they're aiming for an annual release cycle, and they don't want to let the M3 Air/Mini release date run past January. I don't think N3E will be ready for that... but I'm not certain.

 

[Confused-User]

This earlier post makes some points that seem to align with the possibility of the M3 Max SoC being produced with varying features/capacities...?

Sure, and the missing Ultrafusion (assuming it truly is missing) aligns well with name99's speculation.

I was talking more about the possibility of Apple actually doing the harder thing, though - doing another design. It's not at all clear that that's necessary, of course, as name99 pointed out.

 

[Confused-User]

Don’t pat yourself too much on your shoulder. You and some others are speculating just as much about the the M3 architecture although with deeper technical knowledge. As far as I see, there is no solid scientific evidence presented but a try to reverse engineer and explain Apple chips. As long as you do not present the blue print of the SoC design, you are without evidence.[...]

False.

There isn't *conclusive* evidence. But there's plenty of evidence, if you know where and how to look.

Also, there is a meaningful difference between informed speculation and uninformed WAGing. There's been a whole bunch of the latter here recently. And all over the press, honestly, but there's no reason we shouldn't do better than a bunch of half-educated (or less) hacks who get paid by the word.

 

[Apple Knowledge Navigator]

Apple furthermore talked about a new and better cooling system, which is especially needed for the new max chips or to compensate for different core counts with higher frequencies.

They never said it was new and better - they just repeated the 'advanced thermal architecture' spiel that they've said in previous events/releases.

 

[EntropyQ3]

The M3 Max is a slightly more straightforward upgrade, however, M1 Memory Bandwidth Utilization we know that a single P-core can pull over 50 GB/s of bandwidth, so I also dispute the claims that the memory bandwidth limitations aren't going to crop up with the more limited bus width.

With 4 more P-cores, running at higher frequency, and a beefed up GPU also running at higher frequency, memory bandwidth limitations will obviously be more prevalent.
Not on cache resident benchmarks though, so marketing wise, all is good.
As always with memory bandwidth, the impact will be situational.

(Having the RAM as a shared resource between functional units has both upsides and downsides, with contention being a very real concern in more complex scenarios. Benchmarks typically try to avoid the problem in order to get consistent and easy to interpret results, the problem being that they realistically loose in general relevance.)

 

[Confused-User]

I have a more long-range issue with the Pro and Max.

I think that aligning CPU and GPU resources is, in the long run, a mug's game, and that Apple may be pricing itself out of a lot of business. Even business willing to pay Apple's high margins for resources they actually need, because they're unwilling to pay those high margins for resources they really don't need.

This issue is already obvious today. We have people here saying they were happy with the M2 Pro because it had the CPU they wanted, and they didn't want to pay for a Max's GPUs, but now they're unhappy because they can't get their CPU resources without splurging on GPUs they don't need.

Of course the converse is true as well: heavy GPU users may not need all those CPU resources... or might prefer even more GPU cores in lieu of some of the CPU cores.

I've seen a couple comments about thermals and power being a part of this too, but that's not much of an argument because Apple's very good at power gating.

I think there is a path forwards for Apple - move more aggressively into multi-chip, and allow configuration of Macs with user-selected CPU or GPU, er, chiplets (funny word, since they're so huge, but whatever). Say, they make a CPU chiplet with 24P cores, a GPU chiplet with 40 GPU cores, and a "base" chip with roughly what the current Max has. Allow mixing of four of those, and finally you have an expensive Mac Pro that is actually worth all the money you're putting into it. Two, and you've got a Studio that's far more suited for most tasks than the generalist M2 Ultra. This is pretty much what name99's been talking about for a while.

I was honestly hoping for something like that this generation. I guess it's not out of the question yet.

But it would really be better for us, and I think better for Apple as well, if they took this further. Allow configurations at the Mx Max or even Pro level where you can choose more or less CPU and GPU resources. Except, I'm not sure they've got the volume to support the costs of doing this. And that is the heart of the problem, I think.

 

[sv8]

You're welcome. My first reaction to this was, again, that's ridiculous. And honestly I don't think you're right- I think we'll see the Airs + Mini soon, either in November or in January, on N3B.

But it's not really ridiculous. Assuming, as is likely, that they will reimplement the M3/A17P cores in N3E, then... if they're willing to wait for N3E for the Airs and Mini, that could well happen.

The reason I still don't think this is correct is that I think they're aiming for an annual release cycle, and they don't want to let the M3 Air/Mini release date run past January. I don't think N3E will be ready for that... but I'm not certain.

I also don't think A17P will be reimplemented with N3E.

However, I think A18 will become N3E.

Are you think N3E will be a node only for iPhones and iPads?

 

[tenthousandthings]

@sv8 wondered about the Ultra (and possible quad-chip M3) being on N3E. Their reasoning was incorrect, but I noticed something just a little while ago that bears on that.

Looking at the Max's die shot, where is UltraFusion?? Did they just hide it (IIRC they did in some of the early pictures of the M1 Max)? If so it would have to be at the bottom, under the GPUs and SLC/RAM controllers, which is reasonable.

But what if there's another explanation?

They've already changed their pattern (if two generations makes a pattern) - the Pro and Max are clearly quite different from each other, not sharing nearly as much of their design as previous generations. Perhaps the chip that will be the basis of the Ultra is NOT the Max, this generation. Maybe there's no Ultrafusion connector in the M3 Max die shot because it doesn't exist.

This would be pretty surprising - I wouldn't expect them to do a whole new floorplan for chips making up an Ultra, as it would seem to be way too low volume for that. But... They obviously know a lot more than I do, maybe they see a good reason to do this. Maybe they count it as another learning step towards a future full of high-density chiplet interconnects, and therefore worthwhile just for that.

Maybe they need to do more work because they want it to go 4-way as well as 2-way?

Anyway, N3E vs. N3B is a sideshow for this, but: If they have to design M3-class CPU, GPU, and NPU cores for N3E anyway (for the A18, and maybe an M3+?), AND they have to do a separate design for M3 Ultra+ chips, maybe the added cost of redoing the entire M3 Ultra chip on N3E doesn't seem so crazy to them.

If this entire chain of speculation is correct, then we could see N3E M3 Ultras in 2024. Otherwise, it's a near certainty that we'll see M3 Ultras on N3B.

A18 could be on N3P. I'd even say it's likely. The A16 was on N4P, with TSMC giving the same exact volume production estimate ("2H 2022" for N4P and now "2H 2024" for N3P).

That doesn't entirely quash your suggestion, but it does remove an element.

I think a lot of the N3B hand-wringing (I'm not saying you're doing that, or really any of the regulars in this thread) is of the jumping-to-conclusions variety. N3E exists because of FinFlex transistor technology. It's a far more flexible node than N3B, by design. I think it's unlikely any M3 UltraFusion (which, remember, is not standing still -- TSMC has made investments and advances in "fusion" technology as well) silicon would be on N3E, mostly because there is no real advantage in that for Apple. The flexibility of N3E doesn't matter if you already have what you need in N3B.

The importance of N3E and N3P (nobody knows what N3S will be, or even if it will happen) is they are the last FinFET nodes. They are the height of that transistor technology. They will be around for a very long time. N2 and beyond, with "Nanosheet" (gate all around) transistors is next. Apple will stay on the cutting edge, so I'll eat my hat if the M4 presentation at WWDC in 2025 doesn't feature the word "Nanosheet" prominently, but an A18 on N3P could be a long-term stalwart in the iPhone and iPad lineups.

 

[Confused-User]

I think a lot of the N3B hand-wringing (I'm not saying you're doing that, or really any of the regulars in this thread) is of the jumping-to-conclusions variety. N3E exists because of FinFlex transistor technology. It's a far more flexible node than N3B, by design. I think it's unlikely any M3 UltraFusion (which, remember, is not standing still -- TSMC has made investments and advances in "fusion" technology as well) silicon would be on N3E, mostly because there is no real advantage in that for Apple. The flexibility of N3E doesn't matter if you already have what you need in N3B.

The immediate advantage is cost - N3E is cheaper to make because it uses less multipatterning and fewer EUV layers. The biggest disadvantage is notably lower density with FinFlex 3-2 (not so much with 2-1). I haven't heard anything about relative defect rates but they're a year further along the curve with N3B so I can't imagine N3E has a big edge there yet.

But the other advantage of N3E is that it's the process of the future. It's going to be around for *years*, maybe even a decade. N3B, they'd like to wind down as soon as possible. Any design work on N3E will pay dividends in a followup on N3P or N3S, while work on N3B is a dead end. This may matter enough to tip the balance - though maybe that's less convincing now that we know all three dies seen so far are separate designs.

I dunno, I don't think there's enough evidence for even a good guess.

The importance of N3E and N3P (nobody knows what N3S will be, or even if it will happen) is they are the last FinFET nodes. They are the height of that transistor technology. They will be around for a very long time. N2 and beyond, with "Nanosheet" (gate all around) transistors is next. Apple will stay on the cutting edge, so I'll eat my hat if the M4 presentation at WWDC in 2025 doesn't feature the word "Nanosheet" prominently, but an A18 on N3P could be a long-term stalwart in the iPhone and iPad lineups.

Yes, I wrote about the FinFET/GAAFET transition here a couple days ago. I think you're almost right - they may do an A18 (basically an A17P reimplementation) on N3E and an A18Pro on N3P. That seems like a dumb idea to me from a tech standpoint, but also like it might align more closely with their marketing and practice in the last two generations.

 

[Confused-User]

But the other advantage of N3E is that it's the process of the future. It's going to be around for *years*, maybe even a decade. N3B, they'd like to wind down as soon as possible.

Lest anyone misunderstand this... I'm not saying Apple will use N3E for a decade. But the process will likely be in wide use for at least that long. N3B will probably disappear entirely relatively soon.

 

[Xiao_Xi]

N3B, they'd like to wind down as soon as possible.

Is it possible that Apple will stop selling products with TSMC N3E-based SoCs when they are replaced? So, for example, when Apple introduces the M4, it will only sell M2 and M4 based computers.

 

[dugbug]

While we are all handwaving without any data just think: Fully built M3 laptops are coming out next week (two weeks for max) and NO benchmark leaks. Gotta say I'm impressed.

-d

 

[Confused-User]

Is it possible that Apple will stop selling products with TSMC N3E-based SoCs when they are replaced? So, for example, when Apple introduces the M4, it will only sell M2 and M4 based computers.

I think you mean, stop selling N3B-based SoCs. Sure, it's not just possible, it's extremely likely. These aren't iPhones. I don't expect Apple to sell M3 generation Macs once the M4s are out. They did do that with the M1 Air after the M2 came out, but that was unusual. Maaaybe they'll keep an M2 Air or an M3 Air at the bottom of the lineup... who can say?

While we are all handwaving without any data just think: Fully built M3 laptops are coming out next week (two weeks for max) and NO benchmark leaks. Gotta say I'm impressed.

Yes, me too.

I did see one purported leak, claiming to show the base M3 coming within 0.2% of the score of the M2 Pro on MT GB6. If that's true that's *seriously* impressive, but I don't think I believe the source. We should see soon enough.

 

[Pressure]

Geekbench 6 scores are starting coming in for the M3.

CPU
Mac15,3
Single-Core Score 3076
Multi-Core Score 11863

Base frequency 4.05 GHz

Compute
Mac15,3
OpenCL Score 30615