If we’re being honest, most MBA customers aren’t connecting it to an external monitor at all.
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M3 Die Shot suggests display engines take up nearly the same area as P-cores
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Because you are usually connected to power when running external displays. Especially since most displays nowadays are also power supplies. Note that power savings we are talking about is merely .5-1.5 watts - a huge difference running on battery, but not a lot compared to peak system power draw.
True. But once you become someone whose work does require an external (e.g., someone who uses spreadsheets), it's not uncommon to need more than one. And that fraction of external display users is precluded from getting the Air, even if otherwise meets their needs.
The keyword being "fraction". Also remember the same chip also goes to the iPad, where you are not going to be able to attach a 2nd external display without a TB dock, even if the chip allowed you to. Apple may be guilty in many things, but limiting the basic M chip to 2 display buffer is about the closest to being a right call, marketing wise.
Well, fractions can be large
.I'm wondering about business use. I recall one poster who said his boss was thinking of converting to Macs when AS was released, but their budget only allowed for Airs, which would have worked great, except all their workstations use dual monitors. And dual monitors is pretty common in many offices these days.
Note also that the M-chips only go into the iPad Air and iPad Pro. The iPad and iPad Mini use A-chips.
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That's not true though.
He clearly mentions in the video that the area contains two display engines despite only labelling it as a (singular) display engine.
The revised annotated shot of the base M3 looks like this from his video.
It should be possible to make a rough estimate based on comparing memory in the display engines with other memories of known size (such as CPU caches). (Not me though, I don't have the time and also I know how error prone simplistic area estimates can be. In many cases, designers choose different SRAM cells for different memory arrays, based on other requirements, and this means density (bits/mm^2) can change quite a bit between two different memories on the same chip.)
It might be more than 1MB. Those things are huge - each display controller uses the same die area as two P CPU cores.
I think it's unlikely to be eDRAM. That has mostly been an IBM technology. There's probably eDRAM macros available for some TSMC process nodes, but eDRAM is costly. You always need extra process steps, and sometimes they're a bit exotic. IBM's eDRAM is based on etching deep trench capacitors below the "base layer" (where the transistors live), while other kinds of eDRAM build the capacitor in extra metal layers.
1) less power draw while charging means faster charging
2) less power draw in general means less $$$ wasted and less carbon spit into the environment
and honestly, I'd even challenge the assumption that you're usually connected to power when connected to an external display — lots of people aren't. nobody wants their MacBook to waste 40% of battery during a presentation, or maybe even die; and you don't always have the ability to charge during one.
Well, 0.5 to 1.5 watts, given Apple boasts about the best performance per watt, they'd probably want to shave off everything that's not needed.
All fair points. But I think the bottomline is that most of this stuff can should probably be split of on a separate 5N die — would reduce costs and/or free up the space for more interesting stuff, such as more CPU and GPU cores.
Nobody else does it. Why? Because nobody else uses the same design for phones and computers. This extra power consumption, when connected to multiple external monitors, is just a rounding error compared to the monitors' power consumption. Besides people who want to be pedantic about the goodness of lower power consumption in general then have to account for the extra power spent on extra silicon during the manufacturing of the larger chips.
I noticed this also. Must be a more complex protocol to implement than I had previously assumed.
The thing that I'm left wondering about from this video is the mention of "black silicon" or the "seemingly unused" portions of silicon on the chip. That seems expensive in a rising-wafer-cost world.
Does anyone have an idea there? In my layman's thinking, I have an idea that if a company ever started stacking dies (vs using chiplets), they'd need some kind of design for an elevator shaft between floors - not for moving people between floors, but bits.
It appears that there's a decent chunk of SRAM in the unlabeled portions of silicon. There are probably all kinds of things in there.
These “elevators” are called thru silicon vias, or TSVs. You are correct these are used for stacking dies - flash, DRAM, and I think the iPhone mates DRAM die on top of the CPU die already.
Dark silicon has been a major issue for nearly 20 years already. We hit the wall of Dennard scaling in the mid 2000s. But that’s brought us to heterogenous computing accelerators on-die, like dedicated ProRes or H.264 decode hardware.
Dennard scaling - Wikipedia
en.m.wikipedia.org
3840×2160 = 8,294,400 px (100%) 4K UHD
4480×2520 = 11,289,600 px (136.1%) 4.5K iMac
5120×2880 = 14,745,600 px (177.7%) 5K ASD
6016×3384 = 20,358,144 px (245.4%) 6K XDR
Do those Intel display engines support a 6K display at 60 Hz?
Except what he clearly mentions seems wrong. He's saying the Base, Pro, and Max contain 2, 4, and 8 display engines, respectively.
Yet how can the Pro have 4 display engines, when it can only drive 3 monitors? And how can the Max have 8 display engines, when it can only drive 5 monitors?
The more logical explanation is that each of those he has labeled are the individual large display engines (the ones that can drive the 6k externals), and the small display engine on each is unlabeled. Only then do the numbers work. I.e.:
Base: 1 labeled engine; can drive 1 x 6k and 1 x 5k
Pro: 2 labeled engines; can drive 2 x 6k and 1 x 4k
Max: 4 labeled engines; can drive (3 x 6k + 1 x 4k)* and 1 x 4k
*The reason the M3 Max MBP can't do 4 x 6k is that it has only 3 TB ports. But if you look at the M2 Studio, which has 4 TB ports, you'll see it can do 4 x 6k and 1 x 4k
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No one argues that efficiency becomes unimportant when you're plugged in. But you're missing the point here, which is that efficiency becomes much more important when you're not (because then you have the additional concern of battery life, which is not present when plugged).
This doesn't make sense. When you are giving presentations you **are** connected to an external display (the room's main display) and, as you say, you would also likely be connected to power (or at least can easily plug in if needed). Thus you are **agreeing** with the idea that if you're connected to an external you are probably also connected to power (or have access to it), not challenging it.
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My first real "holy **** I'm in the future" moment with Apple Silicon was when I started futzing with the resolution scaling, and then plugged my laptop into an external display.
None of the bouncing around or flickering like on Intel and even PowerPC Macs, just seamless changes. Dang.
If any of that has to do with Apple's oversized display controllers — and again, this is a thing we've been living with for decades — that is absolutely a valid trade-off against running four displays on a flippin' $999 Macbook Air.
None of the bouncing around or flickering like on Intel and even PowerPC Macs, just seamless changes. Dang.
If any of that has to do with Apple's oversized display controllers — and again, this is a thing we've been living with for decades — that is absolutely a valid trade-off against running four displays on a flippin' $999 Macbook Air.
I'm relatively unfamiliar with display hardware at a low level, so I have some questions...
At the moment, it would be prohibitively expensive to buffer an entire frame on-chip. A 6k monitor would require minimally 60MB (more likely 80MB, allowing for 10bpc). This isn't going to change in the next 5 years due to process technology; SRAM scaling is effectively dead, and eDRAM is not likely to be used. However, the industry is moving towards chiplets and complex packaging, so that leads me to wonder if it might not be feasible over time, even for the base Mx chips, to stack enough RAM on top of the base chip to hold entire frame buffers, much like AMD is stacking cache RAM on their X3D CPUs.
Is this likely to be a practical possibility in a few years? ISTM that this would dramatically lower DRAM utilization in the idle case, and would be a not insubstantial reduction in bandwidth use in all cases (5GBps for a 6k60 monitor).
Of course if you're going to do this you might want to move the entire controller off the base chip anyway, which might open up other possibilities.
ISTM that Apple has a big advantage over other architectures if they wanted to do this, because they'd have an easier time knowing when they'd need to copy from system RAM into the display buffer. Assuming they don't make the stacked-chiplet buffer the only buffer - I'm not clear on whether double-buffering would be better or worse here. (I mean, if the CPU or GPU is writing to the display, why even bother writing to main memory, if you have this buffer handy on-chip?)
As you can see I'm well out of my comfort zone here, so if this is utterly stupid feel fee to say so, though I'd prefer to know why.
At the moment, it would be prohibitively expensive to buffer an entire frame on-chip. A 6k monitor would require minimally 60MB (more likely 80MB, allowing for 10bpc). This isn't going to change in the next 5 years due to process technology; SRAM scaling is effectively dead, and eDRAM is not likely to be used. However, the industry is moving towards chiplets and complex packaging, so that leads me to wonder if it might not be feasible over time, even for the base Mx chips, to stack enough RAM on top of the base chip to hold entire frame buffers, much like AMD is stacking cache RAM on their X3D CPUs.
Is this likely to be a practical possibility in a few years? ISTM that this would dramatically lower DRAM utilization in the idle case, and would be a not insubstantial reduction in bandwidth use in all cases (5GBps for a 6k60 monitor).
Of course if you're going to do this you might want to move the entire controller off the base chip anyway, which might open up other possibilities.
ISTM that Apple has a big advantage over other architectures if they wanted to do this, because they'd have an easier time knowing when they'd need to copy from system RAM into the display buffer. Assuming they don't make the stacked-chiplet buffer the only buffer - I'm not clear on whether double-buffering would be better or worse here. (I mean, if the CPU or GPU is writing to the display, why even bother writing to main memory, if you have this buffer handy on-chip?)
As you can see I'm well out of my comfort zone here, so if this is utterly stupid feel fee to say so, though I'd prefer to know why.
Unless you’re giving presentations using a projector. When I finally upgraded from Intel to M3pro that was the first thing I noticed - how incredibly efficient AS is with external display. After 6h of lectures the battery was at 65%, on Intel I had to look for a power socket before 2 hours.
Feature mix seems exactly right to me. I highly doubt people buying base M-series chips are in need of external monitors at all, let alone more than one. Battery life on the other hand is exactly what they need, because its not at a desk plugged in to monitors (and power).
I mean, it's always nice to be able to skip bringing the charger if you're bringing a laptop around a lot. Constantly having to charge was definitely an added inconvenience for me in college.
The key point is not whether or not you are connected to power when using externals, but whether you have easy access to it if needed. And you nearly always do. For instance, whenever I'm giving a lecture using a projector, I can always easily plug in my laptop. That's why the efficiency of the external controller(s) is not as critical as that of the internal.