Confused? You snipped out the leman quote that I was responding to which started off:
previous to that my comment was in response to tenthousandthings comment
Apple reportedly clearly lays out their objective and I'm confused because there is a disconnect between their object and your horizontal expansion proposals? If the length and width of the package is pragmatically fixed, that would be a constraint that Apple didn't want to abandon. The Max package really can't get too much bigger in the MBP 14" logical board.
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The Mac Studio has similar issue with a "double Max" solution for the Ultra. The Ultra's package really can't much bigger.
The die size and the package size are different. The pins to the off-package I/O just tend to take up more space. (so there has been some slop in dies growing while package stays the same time. )
The 2.5D connector is going to buy increased 2-D transistor density how? Let's say more the "I/O" intense stuff off to a N4/N5 die. The 2D area that the I/O is taking up isn't shrinking there ( might be slightly bigger since the smaller fraction of logic in the I/O subsystem might have gotten bigger when backsliding on fab process). If take the "just as big" I/O die and "just as big" logic die and 'glue' them back together with a 2.5D process did the area go down?
If shooting for a radical increase in performance, then probably not. The logic tile/chiplet probably grew a bit even with improved process node ( just as the path Apple has been on with Max growing larger and larger. )
Perhaps if Apple did a N3X logic-only die and a N3P 'the rest" die then perhaps the 2D footprint area could do down. The I/O die isn't so much getting 'cheaper'. It just is more flexible ( stays on Fin-Flex while logic only tosses that flexibility to focus primarily on getting smaller (e.g., reverse the bloat from previous generations). ). To get an aggregate package transistor density increase, it gets hard to include dies that significantly backslide on transistor density and still get a net increase if no stack. The 'other' die(s) with the increase has to make up the backslide deficit before get any net increase.
Apple working with Broadcomm to do a server SoC in 2027 (M6 like time frame) . If it was Max and server were sharing and bigger gaps on I/O that makes more sense to me. But the Pro, SoIC applied to that keeping the costs the same seems like a stretch. (very similr to the Rube Goldberg Mn Extreme rumors that looked more and more expense the more folks tried to push that rock up a hill in rumors. )
Yes, confused. Partly my fault as the original post didn't explicitly specify 2.5D vs 3D connections for the logic dies in part 3. My original post was written before
@leman wrote anything, also I'm pretty sure
@leman was not advocating that CPU and GPU logic dies would be stacked (if I remember Apple's patent he references correctly there might have been some I/O but it was mostly cache structures mentioned being 3D stacked - he can correct me if I'm wrong), and I didn't snip anything out. That's simply how Macrumors' post system works by default. When you reply to a post, quotes inside the quoted posts disappear. Same as when you replied to me, same as when I replied to you just now. As such, I understood where you were coming from and why you had gotten confused between my and
@leman's posts, but I was saying your critique about 3D stacking of CPU and GPU dies didn't actually apply to what I had written originally.
For the post above, I have to admit that
I'm a little confused by the package size critique in your post above. My proposal is not making the Max package size much bigger than it otherwise would be, just whatever additional width the interconnects take which would be negligible compared to the size of the component dies. What one could do with my proposal, is build more flexible solutions than the Ultra (most of which would be smaller!).
Let's do some concrete examples: If a Pro SOC would be made of 1 CPU die + 1 GPU die, then a Max would be 1 CPU die + 2 GPU dies* and an Ultra would be 2 CPUs + 4 GPUs. Same exactly as now, same basic size. However, because you now have (theoretically) the ability to combine any number of these dies together, you could make SOCs
in between an Ultra and a Max such as 1 CPU + 3 GPUs or 2 CPUs + 2 GPUs or etc ... in theory you could even make a smaller "Max" with 2 CPUs + 1 GPU, good for a lot of devs. You could also make different Ultras than just a 2+4. Yes, you could in theory also make larger packages than the Ultra, but which still wouldn't be as big as the fabled "Extreme". The real problem here is logistics, which you and I already pointed out make actually offering a lot of such combinations extremely unlikely, especially as these would almost all be at the high end - Max or above. So while this would be awesome, I already said, even in my initial post, that one should temper expectations as to what Apple would actually offer here even if they introduce tiles, and I also agree with you that even if Apple were to offer more flexible configurations, one should also temper the expectations into what devices those larger SOCs could fit.
Again, Kuo and Ma are the ones asserting that the 2.5Ds packages are coming to the Pro and Max dies in the M5/M6 generation. Indeed,
@tenthousandthings can correct me, but, especially Kuo's research note on the topic asserting that SoIC-mh is coming to the M5 Max/Pro, is why he posted what he posted - wondering if there might be performance benefits. Now, could Apple do any of this without adding extra flexibility to the end package? Of course! And that's more likely. For Apple it may be worth it to simply break out the SLC/IO onto a separate, cheaper die or do stacked SLC (the latter not quite fitting Kuo's note, but still plausible based on the tech). Those ideas, points 1 and 2 in my original post, are what
@leman was referring to as "spot on", not my mixing and matching tiles stacked or not.
Also, depending on the precise manufacturing economics, even just building the Pro/Max/Ultra out of smaller dies than they do currently *might* be cheaper depending on package costs, yield, and die reuse. And thus Apple may simply offer the same solutions they do now just built out of smaller dies without offering all the variations that might, in theory, be viable but would, in practice, be a logistical strain. Lastly, naturally, Kuo and Ma could just be wrong. This is simply my take on the various ways Apple
could reasonably implement advanced packaging for the Pro and Max chips (with some fun potential implications)
if they are right.
*Alternant is a "Pro" die with 1 CPU + 1 GPU on it and then there exists a GPU die that gets tacked on to make a Max. A little less flexible but would have fewer interconnects, so potentially less expensive when building larger units (again depending on the economics of TSMC packaging and yields), also less power, etc ...
