It’s possible, though I’m not holding my breath.
I don’t think Apple has anything to worry about with XE2.
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M4+ Chip Generation - Speculation Megathread [MERGED]
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It’s possible, though I’m not holding my breath.
I don’t think Apple has anything to worry about with XE2.
I'd love to see a return to the more balanced M3 Pro style configuration.
I have an M3 Pro 6P+6e 14" MacBook Pro for work. My typical workload is mixed and keeps the system busy at all times (none of the cores get to park for long!). I love that the peak CPU power draw of this chip is only around 45-50W - switching between moderate load to full load (e.g. a build/compile) frequently doesn't pull enough power to heat it up. It very rarely exceeds lukewarm and the fans are, worst case, a faint whir.
M4 Pro 10P+4e pushed power consumption waaaay higher (~75W for CPU load). It's too high, it can't match the M3 Pro experience. Apple sacrificed quality-of-life for outright performance with that chip 😒
IMO, they should let the Max be the performance at all costs option and rein in the Pro.
The plain Mn to get the lifecycle and volume Apple needs has to fit the requirements of the chain of products it gets passed through. Some substantive limitations are placed on the plain Mn come from the iPad Pro and iPad Air.
The SoC is a succesor to the A1-X line of SoCs. It is just covenient to use it the low end Macs and Vision Pro also.
It would be a change from the past practices ( ignoring mulit stream DP features , trailing behing in implementations) , but it is also a change if their Thunderbolt 'running buddies' is also gone (Intel). If Thunderbolt is 'dead in the water', then continuing the tactic of propping up Thunderbolt by hiding he DisplayPort improvements inside of it would turn into a problem.
DP 2.1 using some lower level TB transport mechanisms. It is just substantially simpiler. It just takes TBv3 40Gb/s bidirectional bandwidth and just points it all outbound ( 4 lanes out instead of splitting them 2&3 in/out ). They can bypass ( if power isolated shutdown) the TB switch and just do pure pass through. TBv5 is higher clocks (more power) and more complexity). Fine if hooking to a display docking station, but if all want to do is talk to plain monitor display.
Intel mobile SoCs already do most of DP 2.1. AMD .. same thing more of DPv2.1 covered. The only laggard holding onto DP v1.4 is Qualcomm. However, they are also completely avoiding Thunderbolt also for the moment. (Understanble and trying to get a Windows market share base to build off of as first priority). Mediatek/Nvidia are covering HDMI 2.1 instead of their N1/GB10 offering, but they are no where near as customer level price point as the plain Mn ( more like a Mn Max ).
Your argument here does not make sense. The existence of the iPad Air has no direct relevance as to what Thunderbolt versions get included the base Mx chips.
The iPad Air does not support Thunderbolt at all, and it doesn't even support USB 4. The iPad Air maxes out at 10 Gbps USB 3, despite having an M3 in it.
i disagree. the M4 mini-pro is not representativ !
it was a bad design choice to put so many P-cores into that housing.
My M4 studio max, 16 cores sucks less Wattage than my M4 mini-pro 14 core did.
Do not take the M4 mini-pro as a reference vs. how the M4s are working.
( i do have an M4mini-base, a Studio-max, and have had the M4mini-pro / and was running the very same tasks on all of them)
the M4 mini-pro is to me a very bad design choice
I'd love to see a return to the more balanced M3 Pro style configuration.
I have an M3 Pro 6P+6e 14" MacBook Pro for work. My typical workload is mixed and keeps the system busy at all times (none of the cores get to park for long!). I love that the peak CPU power draw of this chip is only around 45-50W - switching between moderate load to full load (e.g. a build/compile) frequently doesn't pull enough power to heat it up. It very rarely exceeds lukewarm and the fans are, worst case, a faint whir.
M4 Pro 10P+4e pushed power consumption waaaay higher (~75W for CPU load). It's too high, it can't match the M3 Pro experience. Apple sacrificed quality-of-life for outright performance with that chip
IMO, they should let the Max be the performance at all costs option and rein in the Pro.
I see the appeal for sure. It’s one of the reasons I could see them going for an 8+6 configuration - the binned variant would essentially be this again.
The M4 has 4 TB controllers.
Very unlikely the M5 has less.
Don't confuse the abilities of the Mac with the abilities of the SoC.
Interesting. Apple's Private Cloud Compute is currently using custom Apple Silicon.
https://www.tomshardware.com/desktops/servers/apples-houston-built-ai-servers-now-shipping
https://www.tomshardware.com/desktops/servers/apples-houston-built-ai-servers-now-shipping
The Air's chip do have support for Thunderbolt. Whether Apple turns it on or not does not impact how much die space it soaks up. As the TSMC wafers get more expensive , 'dead' silicon costs more. If Apple doesn't 'turn on' the Thunderbolt system present, they are still paying TSMC for making it.
The M1/M2 has two TB controllers. The M4 has four. Even if Apple turned on the one controller there would have been one dead space TB controller in M1/M2 era and there are now four ( to make iMac look better. and Mini more consistent. ). If turn off all four now have four dead weight controllers. If TBv5 takes up an even bigger die space footprint then you have even more dead space that have to pay for.
As Thunderbolt gets more and more expensive to leave as dead space Apple will likely turn one of them on so they can sell that as a 'value add' to the system. And if Air has just as fast TB as the Pro .... why buy the Pro. ( same reason why iPhone 17 still gets USB 2.0 and iPhone Pro 17 Pro and 16 Pro gets USB 3. ).
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Yet clearly Apple is fine with that for marketing reasons, not only excluding TB support from the iPad Air, but even excluding USB 4 support from it. And of course, that dead space decreases as the node process advances. I don’t expect the Mx series to move beyond 4 controllers in the foreseeable future.
Thus, several years from now, I would expect the Mx to get Thunderbolt 5 support, and perhaps at that time the iPad Air will finally get the USB 4 / Thunderbolt support that’s already been in the Mx chips all along.
Not sure if this is relevant to what you’re discussing, but dead silicon comes back to life when chips with flaws in the TB controllers are used in the iPad Air, chips that can’t be used in Macs. I have no idea how quickly these might pile up but the numbers could be significant over the entire production run of the base M. So you’ve got a bin full of silicon that would otherwise be recycled.
It appears that if connecting the SuperSpeed differential pair (as I recall the name) is more important. Without connecting both pairs, you will only have USB 2.0 connectivity. However, connecting only one pair will provide the speed on the iPad Air and the iPhone Pro. For Thunderbolt and USB4 connectivity, both pairs are necessary.
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Apple is fine with splitting iPad Air from iPad Pro I/O segmentation , but they are likely to abandon that for Mac Air very Mac Pro ? Probably not. The plain Mn SoC has lagged behind the whole time 1-5 generations.
Nope.
AMD Explains the Economics Behind Chiplets for GPUs
AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart...
Pure 'logic' circuits have been going down. A couple of other very necessary things on a A or M series chip have not.
While M1-M4 used increasingly better fab processes, the die sizes actually got bigger.
M1 approx 119 mm^2
M2 approx 140 mm^2 (admmitedly not much of shrink here)
M3 approx 168 mm^2
M4 approx 167 mm^2 ( somewhat of backslide on SRAM/Memory here being offset by probably better logic optimization)
The M5 has twice as many TB controllers. It is not going to be shocking at all if the M5 has just as large, if not larger, than the M4.
The Thunderbolt subsystem has some logic subcomponents, but the primary task of Thunderbolt is to communicate off chip to relatively very far away devices. That will drag in I/O aspects which is getting more expensive as wafer costs go substantively higher.
I would be surprised if it stays at 4. Some 'inspired' redesign of the iMac comes out with just 3 ports, it could very easily backslide to three. If the M5 is even bigger than the M4 then that is on the table.
If Apple is a big fan of I/O segmentation then how to they move TBv5 down if there is not TBv5+ to put the Pro line up? If the vast majority of PC market is stopping at TBv4 (or worse) then TBv5 would remain all that was necessary to segment the Pro line up at a higher level.
The plain Mn is small eough that applying chiplets to it is somewhat questionable. Even thought the chip stacking stuff ( extreme minimal distance communication) still has some overhead. And it is more complex (costs more) if can get the plain Mn back into the 135-155 mm^2 zone. The smaller the die, the less sense it makes to break it apart.
M1 is TSMC N5.Apple is fine with splitting iPad Air from iPad Pro I/O segmentation , but they are likely to abandon that for Mac Air very Mac Pro ? Probably not. The plain Mn SoC has lagged behind the whole time 1-5 generations.
Nope.
AMD Explains the Economics Behind Chiplets for GPUs
AMD, in its technical presentation for the new Radeon RX 7900 series "Navi 31" GPU, gave us an elaborate explanation on why it had to take the chiplets route for high-end GPUs, devices that are far more complex than CPUs. The company also enlightened us on what sets chiplet-based packages apart...www.techpowerup.com
Pure 'logic' circuits have been going down. A couple of other very necessary things on a A or M series chip have not.
While M1-M4 used increasingly better fab processes, the die sizes actually got bigger.
M1 approx 119 mm^2
M2 approx 140 mm^2 (admmitedly not much of shrink here)
M3 approx 168 mm^2
M4 approx 167 mm^2 ( somewhat of backslide on SRAM/Memory here being offset by probably better logic optimization)
The M5 has twice as many TB controllers. It is not going to be shocking at all if the M5 has just as large, if not larger, than the M4.
The Thunderbolt subsystem has some logic subcomponents, but the primary task of Thunderbolt is to communicate off chip to relatively very far away devices. That will drag in I/O aspects which is getting more expensive as wafer costs go substantively higher.
I would be surprised if it stays at 4. Some 'inspired' redesign of the iMac comes out with just 3 ports, it could very easily backslide to three. If the M5 is even bigger than the M4 then that is on the table.
If Apple is a big fan of I/O segmentation then how to they move TBv5 down if there is not TBv5+ to put the Pro line up? If the vast majority of PC market is stopping at TBv4 (or worse) then TBv5 would remain all that was necessary to segment the Pro line up at a higher level.
The plain Mn is small eough that applying chiplets to it is somewhat questionable. Even thought the chip stacking stuff ( extreme minimal distance communication) still has some overhead. And it is more complex (costs more) if can get the plain Mn back into the 135-155 mm^2 zone. The smaller the die, the less sense it makes to break it apart.
M2 is TSMC N5P.
M3 is TSMC N3B.
M4 is TSMC N3E.
M5 is TSMC N3P.
That's just a single node shrink between all five generations of Apple Silicon.
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M1 - 16 billion transistors
M2 - 20 billion transistors
M3 - 25 billion transistors
M4 - 28 billion transistors
M5 - ??
M2 - 20 billion transistors
M3 - 25 billion transistors
M4 - 28 billion transistors
M5 - ??
It helps offset the costs to pull some back out of the recycle bin, but the defect has to hit in just the right places. ( MacBook Pro's with Three TB ports and 4 controllers can somewhat pull similar trick. If the DisplayPort pass thru still works, then they can use that as HDMI feed. )
But with 2 (or more) TB controllers are really going to have two dead ones? There are redundant function units here. The redundant one(s) that you still don't use is still dead space.
M1 vs M2 vs M3 vs M4 vs M5 - Low End Mac
With the release of the new M5 MacBook Pro and iPad Pro on October 22nd, we’re 5 generations into the Apple Silicon lineup, marking half a decade since Apple Silicon became available for consumers. . . . Although the new chip was announced quietly, it’s hard to remain silent about something – it...
lowendmac.com
That seems likely for the second generation of PCC servers. The Arizona plant (Fab 21) is scheduled to open its 3nm facility ("phase 2") for volume production in 2028. So it would be the same pattern as the M2 Ultra on N5P thought to be used in the first generation of PCC servers. The first three years of M5 Ultra production on N3P will happen in Taiwan, then at least some of that will move to Arizona.
I think the bellwether will be the Mac Pro. It will get M5 and be assembled in Texas like the servers. 2028 is the earliest you'd see Fab 21 silicon inside a 2026 M5 Mac Pro (or a M5 custom PCC server), but if they continue to use the 2019 chassis then it will likely still be assembled in Austin.
Ohhh so the servers will be composed by M5 Ultra chips, not regular M5… okay. I don’t know why I was thinking in hundreds or thousands of M5 chips running in parallel.
I don’t remember where the M2 Ultra claim originates, but I think it is a reliable source.
Apple to Power AI Tools With In-House Server Chips This Year
Apple Inc. will deliver some of its upcoming artificial intelligence features this year via data centers equipped with its own in-house processors, part of a sweeping effort to infuse its devices with AI capabilities.
www.bloomberg.com
Updating CPU frequencies for Apple silicon Macs
A call for help: can you help complete this table of all the CPU core frequencies of M-series chips? M3 Ultra and M5 values are requested, please.
eclecticlight.co