chars1ub0w
macrumors 6502a
With the M6 reportedly not using TSMC’s best 2nm process (N2 vs. N2P node), will M6 frequencies not receive much of an uptick? The M3 to M4 jump was huge.
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M4+ Chip Generation - Speculation Megathread [MERGED]
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IvyKing
macrumors 6502a
About to slow down??? Between 1980 and say 2003, processor speeds went from 8 MHz to 1+ GHz, for over a factor of 100 increase in speed. Since then we've seen maybe a factor of 3 - 4 increase. The major increase in throughput has been a combination of executing more instructions per clock on a single core and more cores running in parallel.
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First public macOS kernel memory corruption exploit on Apple M5
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blog.calif.io
throAU
macrumors G4
First public macOS kernel memory corruption exploit on Apple M5
Apple spent five years building hardware and software to make memory corruption exploits dramatically harder. Our engineers, working together with Mythos Preview, built a working exploit in five days.
Nothing is ever 100% secure.
Think of ANY additional feature as an additional hurdle. This does not make the advancements that Apple have made pointless, and you can bet that lessons learned will go into M6, and lessons learned there into M7, etc.
M4 and previous generation are much easier to exploit.
It's more than just that. Obviously until we know details all one can do is speculate, but I suspect this is much like the ForcedEntry exploit.
Recall that one type of zero-click exploit against messages was to craft media files (JPEG, PDF, GIF, whatever) that exploited a bug in the code parsing such media files. Once the parsing goes wrong, you have control of the Messages process which at the very least gives you access to the messages and contacts of the victim.
Apple supposedly fixed this by creating a second process, called Blastdoor, in which media are parsed. So if there's a bug in parsing (and there will be, for a while, because parsing these formats can be so tricky) all you achieve is control of the Blastdoor process which has few permissions and can't do very much of interest.
Even so, soon after Blastdoor was released, an exploit named ForcedEntry was able to gain access into Messages. How?
Well, not EVERY media file was routed through Blastdoor! For reasons that, in retrospect, look dumb and foolish, GIFs used in a very particular context were considered trustworthy (eg GIF is not that complex a format to parse) and so were still parsed inside the Messages process, not via Blastdoor. So when a Trojan GIF was encountered, game over! (And in fact the underlying intuition, that GIF is simple and safe, may well have been correct. The problem is that not everything that claims to be GIF is in fact GIF! The Trojan .gif file was treated as gif by Messages, but then recognize by the parsing code as a mislabeled .TIFF file. Which could exploit bugs in TIFF parsing...)
Point is, locks only work if you lock EVERY door in the house. Blastdoor was a good idea, foiled by bad assumptions in the surrounding code. As far as I know, after the GIF foolishness that allowed for ForcedEntry was shut down, Messages and Blastdoor have not been cracked since.
My guess is we have the same thing here. The overall architecture of MTE (both the hardware side and the OS side) are correct, but to be safe, every part of the system has to use MTE. What I expect we will find is something like some driver was
1. not compiled with MTE AND
2. not 100% confined to userspace. (Most drivers are now in userspace so that even if they are exploited, like Blastdoor, all that exploit gets you is control of that userspace process which has limited capabilities and permissions. Those that have to communicate with the kernel are supposed to use something like XPC that limits their ability to manipulate kernel memory.)
We'll probably find some driver that's ten years old and hasn't been touched in eight years, that people assumed was safe [like GIF], so not worth retrofitting with MTE and XPC, but the assumption of safety [like GIF] could be worked around via "lying" to the system (eg maybe a driver that decodes JPEG in HW, but you give it a malformed JPEG file...)
Sydde
macrumors 68030
The original Apple II had a 1MHz 8-bit Processor in the late '70s; the 64-bit PowerMac G5 reached 2.7GHz just under 30 years later. That is a factor of 2700, and nearly 9 times faster than the G3 iMac about 8 years earlier. But, you have to consider scale: 5GHz is slightly less of an overall jump compared to the total gain of the first 30 years.
We have gone from µ-scale ICs to lower n-scale ICs, and the issues with mastering those smaller scales are non-trivial. In total gain, we are a little ahead of where we were, but we are also reaching the lower limit. At 1Å, the process will be right on top of the actual size of the atom of silicon. Most gains henceforth will be in operational design, and it is unlikely that clock speeds will sustainably pass the 7GHz mark.
IvyKing
macrumors 6502a
The Apple II was announced at the "First West Coast Computer Faire" in April 1977 - I've got one of the original flyers from the event somewhere in my collection. My recollection was that 2MHz and possibly 4MHz 8080's and Z-80's were being sold at that time. Seattle Computer Products was working on their 8 MHz 8086 board in 1979, and they were running MS's standalone disk BASIC on it in Nov 1979. Their 8086 system was offered for sale in 1980, hence my 8MHz figure for 1980. Going back a few more years, the 8008 had a sub 1MHz clock speed.
Sun's Niagara processor was a bit ahead of its time with the focus on throughput as opposed to single core performance. A book on Posix threads published by Sun in the late 90's specifically mentioned that threads only made sense if the code was intended to run on a multiprocessor (or multi-core) machine. An early example of running multiple instructions at the same time was the mid-60's CDC6600 that had multiple specialized functional units so more than 1 instruction could be executed at the same time.
One limit on processor speed comes from the on-chip "wires" connecting the various circuits act as RC transmission lines, where the propagation times go up with the square of the distance. This gets worse as the features shrink.
Another issue is that the feature size is approaching the "uncertainty" (indeterminate is more accurate) limit, where conductors and insulators are no longer well defined.
On another note, the Apple I had the option of using a 6800 as well as the 6502. I wonder if things would have turned out a bit differently if the Apple II used the 6800. Microware's OS-9 could multitask on a 6809 micro, such as the Tandy Color Computer. The downside would have been the lack of a compatible upgrade path as Intel had with the 8086 to the 80286 and even better the 80386.
Sydde
macrumors 68030
The 6502 was low-cost, simple and fast. The advantages of the 6800 were minimal in comparison. If multitasking were a real consideration for home computers at the time, building the basic circuitry to support it (op-code parsing for dynamic z-page, stack and banked memory) would not have been much of a lift. The 6800 was good but kind of clunky in comparison.
At present, it looks like CPU performance has itself hit a different sort of wall. For most tasks, greater efficiency is not really needed. 4GHz, 5GHz, 6GHz, there is not really that much to gain. The serious work is the stuff that gets done in the GPU, and raising the clock is not necessarily the best approach for embarrassingly parallel work, or even moderately parallel work.
Populus
macrumors G3
So, the next step in the Apple Silicon history is the M6. Lots of changes coming to the M6 thanks to the adoption of TSMCs new 2nm process.
But that’s not what I wanted to ask.
As some of you may know, the way the chips are going to be packed is different. They will be able to pack componentes such as the RAM modules on top of the main die, instead of to the side.
This opens a question for me. Manufacturers seem pretty confident to put components on top of the many die, but what about heat?
In theory heat will dissipate vertically from the main die, throughout the RAM (which also generates heat) to the point of heat exchange, such as the heatpipe.
Will this upcoming architecture harm the die in the long term due to a poorer heat dissipation? If I’m not mistaken, the RAM will be sandwiched between the die and the heat-pipe that carries away the heat.
The M6 is expected to be mounted like that. What do you think about this?
But that’s not what I wanted to ask.
As some of you may know, the way the chips are going to be packed is different. They will be able to pack componentes such as the RAM modules on top of the main die, instead of to the side.
This opens a question for me. Manufacturers seem pretty confident to put components on top of the many die, but what about heat?
In theory heat will dissipate vertically from the main die, throughout the RAM (which also generates heat) to the point of heat exchange, such as the heatpipe.
Will this upcoming architecture harm the die in the long term due to a poorer heat dissipation? If I’m not mistaken, the RAM will be sandwiched between the die and the heat-pipe that carries away the heat.
The M6 is expected to be mounted like that. What do you think about this?
Luftkopf
macrumors 68000
I have been wondering the same thing. I’m sure they’ve done a lot of engineering on it, but I still wonder.
diamond.g
macrumors G5
i imagine it will be similar to the thermal/performance difference between AMD 7000/9000 X3D chiplets.
There is little to no evidence for that. This has been covered before.
First , this hand waving is typically supposedly motivated by the new TSMC SoIC packaging technology. Yet on TSMC's own page about SoiC most of the examples are horizontal, not vertical placement.
TSMC-SoIC® - Taiwan Semiconductor Manufacturing Company Limited
The M5 Pro/Max came out and are all reports ... horizontal. For example.
Apple M5 Pro Chip Teardown Analysis: Apple Silicon Chiplet Era Beckons
Counterpoint's in-chip teardown analysis reveals how Apple's M5 Pro ushers in the chiplet era with a dual-die architecture, unified memory support, advanced packaging technology, and enhanced AI…
counterpointresearch.com
Second, "RAM Modules" is suggestive of the DRAM modules that Apple uses in M-series. That isn't really covered by the SoIC example above either. Those modules are already stacked several layers high just on their one. There is no multiple vertical stacking in the TSMC examples. The relatively very large L3 Cache that Apple uses isn't really a "RAM module". At present it is deeply integrated into the chip. It is a distinct functional subunit of the chip but 'module' is not particularly accurate at all.
Conceptually Apple could take either the Cache or the. Cache+Memory controller and put that is a separate layer. ( akin to AMD's. V-Cache on Zen chips or. the cache+HBM controller on the current MI-x00 chips. ). But that won't be lots of RAM. It is more packing more stuff into the same footprint. ( If Apple layer more of the large L3 cache into another layer than the AI cores could expand into that vacuum. ).
The current horizontal CPU and GPU chiplets wouldn't get stacked. The GPU chiplet might get 'taller' (and more expensive ) in that context.
In the examples about there are no high performance logic on high performance logic examples. SoCs generally not uniform heat generators. Some parts generate more heat than others. If prune off a 'cooler' part and only stack that one deep , then manage the heat issue.
However, stacked chips generating heat. That isn't particularly new at all. As mention the M-series RAM modules have been sticked dies the whole time for years.
It won't be too surprising if Apple shifted the An-Pro SoC to horizontal from the now vertical. That stacking of multiple layers of RAM on top A-series isn't helping it get to top performance. The size creep on the top end iPhones keeps allowing incrementally larger logic board inside the phone (if could get batteries to stop also getting bigger. 🙂 )
But even if keep the stacked DRAM on top design, it isn't any new thermal hurdle that the A-series wasn't already laboring under. The length of the wiring to the DRAM and pad connections are just different.
The plain M6 very likely looks list the plain M5, M4 , M3 , M2 , M1. It is likely too small to be further decomposed into a chiplet design ( via TSMC SoIC technology).
Stacking the DRAM modules for the plain Mn just places it in the same thermal box as the A-series has been in. Apple dumped that for the A1n-X series long ago before the M-seres designation came about. Nothing really has changed since there is no major logic board footprint shrinkage demanded from where the plain M-series is placed now.
Reportedly there are not M6 Pro/Max variants that might be big enough to deserve chiplet decomposition so they also probably are not getting the SoIC vertical treament.
M7 Pro/Max may or may not. Depends upon how economically the M5 Pro/Max packaging worked out. If still very much in the oversubscribed state at TSMC then multiple step packaging ( GPU higher then repeat horizontal for CPU) may not be worth it.
The one thing I would add to this is that synthetic diamonds (and specifically diamond film) is a hot topic right now. Sure, you can get excited about the implications for wedding rings, or Botswana, if that's your thing, but the more interesting element is the role these might have in limiting the thermal overload of future designs by being better able to conduct the heat away from hot spots that will be covered by eg RAM.
This is basically lab tech right now, but lab tech in the process of being commercialized. One expects (for the obvious reasons) that we'll first see deployment in massive GPU type designs, but maybe not? Maybe the first deployments will work better on small areas (just 10mm^2 or so) and will actually be a better cost/value tradeoff for someone like Apple than someone like nVidia?
Populus
macrumors G3
I didn’t know diamond was so highly conductive, but still, more than copper? I guess the thing with diamond is that it can transfer heat without being electrically conductive?
IvyKing
macrumors 6502a
Diamond is a lot more thermally conductive than copper due to heat being transferred by phonons. Graphene is also more thermally conductive than copper when the transfer is parallel with the plane.
Diamonds ... that is going to make the SoCs more affordable with low energy inputs for component production. 🙂
This may help in keeping heat away from photonics chiplets. The datacenter crowd (Nviedia etc) might get here first.
IvyKing
macrumors 6502a
IIRC, diamond heat spreaders have been used with laser diodes for better control of temperature. Some applications call for maintaining diode temperature to a fraction of a degree to maintain wavelength.
Graphene is being used for heat spreaders.
ClaraStahlbaum
macrumors 6502a
What will be the real difference between the M4 and M6 chips? I am thinking about possibly upgrading to the M6 Mac Mini when that comes out.
Vincent Hanna
Suspended
I’m no chip expert, but M4 to M6 will have at least these three huge improvements:
1. 2nm node for much greater power efficiency.
2. An improved version of the GPU jump we got with the M5 with its per-core neural accelerators.
3. Greatly improved memory bandwidth.
1. 2nm node for much greater power efficiency.
2. An improved version of the GPU jump we got with the M5 with its per-core neural accelerators.
3. Greatly improved memory bandwidth.
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Both of which likely cost more. The N2 wafers cost more than the ones used for M4. It is likely the die area used is approximately the same ( since Apple will be after performance increases. So 'more stuff' offsets shrink). Bleeding edge memory likely also costs more.
So up in the air whether. Pref/$ is improving here or not. If the M4 system is fast enough then could be paying more for bragging rights than in the past.
Probably not getting a bump in CPU core counts. So probably not a huge spike past cumulative 2 generation improvements Apple has rolled out in the past.
Probably historical average increment on GPU also ( since put in a larger than usual effort on M5's GPUs.). More stuff coupled to more bandwidth gets an increase.
More the decent chance the MBP M6 ships far enough before the Mini M6 that you can just simply wait for the MBP variant to arrive and just look at the numbers. Prediction isn't particularly necessary if cannot buy the Mini until well after the M6 appears on the market.
tenthousandthings
Contributor
Perhaps I’m misremembering, but isn’t there a mainstream rumor that there will be no M6 Pro/Max? If so, then there may never be an M6 Mini.
I think the biggest area for improvement with A20/M6 is the introduction of hybrid WMCM packaging. We know TSMC is “all-in” with it, but I don’t think it’s clear exactly how it will change iPhone/iPad silicon. I would expect Apple to focus on improved thermals.