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1d1otic

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Probably a new chip design but not close to what M6 series supposed to use by manufacturing all cores and controllers and then merge them together. Probably need to check the die image.
 

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manufacturing all cores and controllers and then merge them together
I don't think they'll be manufactering individual cores and sticking them all together, they're not discrete enough and the interface overhead would be far too high. At most what we'd likely see from any company would be a cluster of cores (CPU, GPU, NPU, whatever), or media engines that can be combined into a single SoC. Much like what AMD has already been doing.

But the release sounds like what's actually happening, they're combining multiple dies. My guess is they're binning the base M5 dies?
 
I don't think they'll be manufactering individual cores and sticking them all together, they're not discrete enough and the interface overhead would be far too high. At most what we'd likely see from any company would be a cluster of cores (CPU, GPU, NPU, whatever), or media engines that can be combined into a single SoC. Much like what AMD has already been doing.

But the release sounds like what's actually happening, they're combining multiple dies. My guess is they're binning the base M5 dies?

Kinda confirmed then.
 
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Makes me wonder if there's still going to be an M5 Ultra chip, or if the "Max" moniker ends up being the new "Ultra".

I sure hope not.
 


If side-effect of splitting the Max die because it got too big could in some sense label this ‘Fission’ as opposed to to Fusion. 😀

Going to Super + Performance core looks to have made made the aggregate die size get larger .


The one labeling question mark is for the media engine being on the CPU ‘chiplet’ ( a lot less of a too chunky chiplet but more deliberate function decomposition). The Max packages have two video encode/decode engines .
Could be the common base one is on CPU chiplet and augment on is larger GPU chiplet because more room.
( optionally extra present on CPU chiplet but binned off because not enough bandwidth to go around ) .
 
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Makes me wonder if there's still going to be an M5 Ultra chip, or if the "Max" moniker ends up being the new "Ultra".

I sure hope not.

Ultra in the previous fashion of 2x the Max die? I suspect that is gone. In part if the monolithic Max got so large it spit apart, that means the current style max are even bigger aggregate area and hence more expensive. 2x more expensive is even more expensive .

The Mac Studio has a fixed size 2D logic board footprint. They can incrementally reshuffle the integration of the support chips to save some space , but the Ultra can’t keep growing like the Blob .

One approach would be to get an incrementally larger ‘ desktop ‘ CPU chiplet ( if this CPU chiplet is stripped to 3 Thunderbolt controllers then get back to four (**). Strip out the eDP for embedded display . Plus incrementally add CPU cores if there is room ) and an incrementally larger GPU chiplet ( with additional memory controller. The old M3/M4 max size but all the non GPU+meprt still ejected.) . Something that is bigger but not 2x more aggregate die area. .

Pair the boosted CPU chiplet with ‘laptop’ large GPU chiplet for a ‘desktop’ Max . Pair the boosted CPU and GPU chiplets for new ‘Ultra’ .

The Max SoC can’t keep getting larger and larger either. But the desktops Studio ( and Mac Pro if keep around ) can have looser 2D footprint constraints . ( if keeping Mac Pro stick a small, ‘ box with slots ‘ I/O provisioning chiplet in between CPU and GPU . That way don’t have to load up desktop/laptop CPU chiplet with I/O that only MacPro can use… wasting lots of space in those other systems’ SoC . ) .


P.S.
**. Or go up to six TB controllers so that Mac Studio is consistent in Max/Ultra versions of having same Type C ports all around.
 
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If side-effect of splitting the Max die because it got too big could in some sense label this ‘Fission’ as opposed to to Fusion. 😀

Going to Super + Performance core looks to have made made the aggregate die size get larger .


The one labeling question mark is for the media engine being on the CPU ‘chiplet’ ( a lot less of a too chunky chiplet but more deliberate function decomposition). The Max packages have two video encode/decode engines .
Could be the common base one is on CPU chiplet and augment on is larger GPU chiplet because more room.
( optionally extra present on CPU chiplet but binned off because not enough bandwidth to go around ) .
It's an artistic render, there aren't any public die shots yet and you can tell they just took the image on the far right and overlayed an image of interconnect onto it for the middle image. Having said that, it'll probably end up looking something like that.
 
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Ultra in the previous fashion of 2x the Max die? I suspect that is gone. In part if the monolithic Max got so large it spit apart, that means the current style max are even bigger aggregate area and hence more expensive. 2x more expensive is even more expensive .

This is, in part, why I'm waiting for the refreshed Mac Studio to see what they end up doing instead of going with a MBP M5 Max.

I'm currently using my MBP M3 Pro in clamshell as my desktop, but get concerned about cooling when doing AI heavy workloads and it ramps up to over 90c.
 
It's an artistic render, there aren't any public die shots yet

Which is odd given Apple past introduction materials . I get impression there is some ‘secret sauce’ or surprise variant that has to do with the Mac Studio release that they want to more dramtically reveal. Retroactively renamin Super cores is a similar “ have to save it for the grand unveil” tactics. Probably better than the ‘it is not there’ …’now it is’ photoshopped of the UltraFusion connector they have done before. If don’t want to show several parts of the picture , just don’t show the whole thing .
 
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Which is odd given Apple past introduction materials . I get impression there is some ‘secret sauce’ or surprise variant that has to do with the Mac Studio release that they want to more dramtically reveal. Retroactively renamin Super cores is a similar “ have to save it for the grand unveil” tactics. Probably better than the ‘it is not there’ …’now it is’ photoshopped of the UltraFusion connector they have done before. If don’t want to show several parts of the picture , just don’t show the whole thing .

Just to make it clear, I don't believe that the image posted here comes from Apple. It seems to be an artistic representation done by some third party.
 
Just to make it clear, I don't believe that the image posted here comes from Apple. It seems to be an artistic representation done by some third party.

Just to be clear I was referring to Apple's less than truthful images that they released that photoshopped out info for M1/M2 Max.

I get that this some is synthesized because Apple didn't ship any images ( photoshopped or not).
 
Ultra in the previous fashion of 2x the Max die? I suspect that is gone. In part if the monolithic Max got so large it spit apart, that means the current style max are even bigger aggregate area and hence more expensive. 2x more expensive is even more expensive .

They could do two "CPU die" and one or two "big GPU die" in an Ultra, if the interface supports more than one connection.

Heck, they could make it individually configurable per customer workload requirements. Instead of just "Max with slightly fewer or more cores" and "Ultra with slightly fewer or more cores" that is just two of the Max chips, they could do "1, 2, or 3 CPU blocks, plus 1, 2 or 3 GPU blocks, 4 blocks total". If you have a CPU-heavy workload, you could pick a 3 CPU, 1 GPU configuration; if you have a GPU-heavy workload, you could do 1 CPU, 3 GPU. A lot cheaper for Apple to have just the few CPU and few GPU configurations from the wafer fabs that they mix-and-match on the package to create many different tiers.
 
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One thing those renders do not account for is the concept of vertical stacking on the die. This is something that has been hinted at for future M-series silicon, and something TSMC has experience with with respect to the AMD Ryzen x3D CPUs (which stack additional vcache on a CCD). Stacking would make those concerns about die size largely irrelevant.
 
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