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MicroProcessor Forum 2002

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Apr 12, 2001
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This Infoworld article discusses the upcoming Microprocessor Forum that begins on October 14th.

The senior editor of the Microprocessor Report speculates that IBM's new PowerPC will be used by Apple, and targets it in late 2003:

"(The PowerPC) is the answer to the Macintosh question of 'Where do we go from here?' " Krewell said. The processor will ship in the second half of 2003, he said.
Click to expand...

This conference gained interest after notes that IBM would be providing details surrounding a 64-Bit PowerPC with later rumors that Apple and IBM were in talks about the processor. Apple has traditionally been very secretive about such details, so full disclosure about IBM/Apple details are unlikely at the conference.
 
Article Link
https://www.macrumors.com/2002/10/06/microprocessor-forum-2002/
Although I am pleased that it looks like the Mac will be getting a good processor, I am a little disappointed to see that it probably wont be available until Late 2003.
 
Although I am pleased that it looks like the Mac will be getting a good processor, I am a little disappointed to see that it probably wont be available until Late 2003.
Click to expand...

Hence the reason I usually come in here and put this nonsense down. Heck, we don't even know IF this processor--assuming it really exists--will ever find its way into Macs. And even if it does, we've been hearing of speeds of 1.6-2.0GHz. Wowee. Intel and AMD will probably be closing in on 4GHz at that point, but clock speed doesn't count, right?
 
Originally posted by Kethoticus


Hence the reason I usually come in here and put this nonsense down. Heck, we don't even know IF this processor--assuming it really exists--will ever find its way into Macs. And even if it does, we've been hearing of speeds of 1.6-2.0GHz. Wowee. Intel and AMD will probably be closing in on 4GHz at that point, but clock speed doesn't count, right?
Click to expand...
I think we all know that Mhz is not a good indicator of speed. I dont really mind what Mhz we get, as long as it gives true performance.
 
puzzle pieces

Its all starting to come together

The mac community has been acting more and more like wall street investors - If its not happening this quarter then the company is in trouble. Well, try and see the big picture.

G4 sales slow to a trickle, no real improvements to speak of. But come january you cant boot 9, so that should squeeze a few more units out of us. Then...

New Moto chips in the new year - G4 7/8 for the powermac and XServe

Then comes the IBM G5 at MWNY

The moto chips filter down to the consumer/portable end

Everyones happy, Apple, IBM, Moto

and specially me

This emac will keep me going for 9 months

Am I right People?

Then Apple does a reverse takeover of Disney and its game on....
 
Originally posted by Kethoticus
And even if it does, we've been hearing of speeds of 1.6-2.0GHz. Wowee. Intel and AMD will probably be closing in on 4GHz at that point, but clock speed doesn't count, right?
Click to expand...

Clock rate counts, as does memory bandwidth the number of instructions executed for each clock tick and what each instruction achieves, along with I/D cache sizes, the latencies of the memory system and each of the caches (L1, L2 and L3 these days), along with branch prediction accuracy, the number of execution units available, etc, etc.

So yes, clock rate counts. But it is only one of a large number of factors that contributes to how much useful work can be done each second. As I see it at present, the real weakness that most needs to be addressed to improve the performance of Macs is to improve the memory bandwidth and decrease the memory latency. These are both areas where the Power4 design from IBM is extremely impressive. This is why there is such potential for GPUL (or whatever).
 
Originally posted by Kethoticus


Hence the reason I usually come in here and put this nonsense down. Heck, we don't even know IF this processor--assuming it really exists--will ever find its way into Macs. And even if it does, we've been hearing of speeds of 1.6-2.0GHz. Wowee. Intel and AMD will probably be closing in on 4GHz at that point, but clock speed doesn't count, right?
Click to expand...

Well AMD/Intel 64bit CPUs won't be reaching 4 GHz anytime soon so I wouldn't worry... and yeah clockspeed doesn't mean a hill of beans if you don't have a well designed I/O throughput!
 
If the CPU reaches Apple, their marketing department is going to have one tough message to communicate.

Not only will they have to communicate the idea of a the Mhz Myth, they will also need to communicate the idea of 32bit vs 64bit. :)
 
Originally posted by Rocketman


Which translates to CPU's in 2004. You will need patience :)
Click to expand...
I hope I wont need to buy a new computer for a long time! I got my Dual 1Ghz, 1Gig of RAM in March.
 
photon processor

did you hear about this?
in 4 or5 years it is supposed to be working.
it will work in tetrabytes .it will work in a computer with no hard drive , but a protein cube.
it is an effort of apple and ibm.
 
in 4 or 5 years...

Wanna bet about seeing this in 4-5 years? If so, how much longer do you think it would be before it starts to catch up to current silicon processes?

Photon is not a 4-5 year deal. It's 20 years if we're lucky.
 
Apple will be introducing an "ALL NEW" G4 chip from IBM that beats the socks off of Intel. IBM's new chip is clocked at a whoping 1.5 Ghtz, But don't let the clock speed fool you. I know that Intel has a 4 Ghtz in the making but clock speed doesnt really mean anything. Now the new chip will be introduced sometime in late 2005 maybe early 2006. There will be different prince ranges... ex... the single processor 1.25 Ghtz for $2000.00 the Dual Processor 1.37 Ghtz for $3000.00 and the dual processor 1.5 Ghtz for $8900.00"

I know I'm being a "smart alec" I just want a new, fast chip!!!!:D
 
Oh well. I guess that we mac users just can't get a break on our processors, all we want is just one good one! Just one!


Stupid intel with their 4Ghz processors...:(
 
Currently...

...here's the situation
Code: 
G4                             P4              POWER4
3 instructions/cycle           3                 8
1.25 Billion cycles/second    2.8               1.4
1 FP Unit                   1+1 FP Load/Store    2
32k/32k L1 cache           ? small             32/32?
256k on chip L2 cache        512k on chip      128MB+
~1.34GB/sec bus bandwidth     4.2               10+?
no out of order exectution    OOOE             OOOE
2MB L3 cache                  none             none
Altivec (4 pipeline)     SSE/MMX(shared)       none
No x86 decode step          x86 decode         no
7 stage pipeline              20               10?
Single core                  single            dual
dual-processor               single            multi
.18 micron SOI                .13              .18

Here's what I think the "GPUL" will have
8
1.4-2
2
32/32
512k on chip
6.4 (confirmed)
OOOE
?
Altivec (?)
no
?
single
dual, maybe multi eventually
.13 SOI, maybe .09 SOI

Basically, take a POWER4, slash the 128MB+ L2 cache, cut the bus bandwidth, remove the second core, and put it on a smaller manufacturing process. Then add Altivec and move the L2 cache on chip. The last two would cost more, but the first four would drastically reduce the price. If I'm anywhere close to correct, this chip will be ***fast***.

note: the question mark next to Altivec isn't about whether the GPUL will have it, it's about whether it will share execution units like the P4, or have seperate ones like the G4.
 
Code: 
G4                             P4              POWER4       GPUL
3 instructions/cycle           3                 8            8
1.25 Billion cycles/second    2.8               1.4         1.4-2
1 FP Unit                   1+1 FP Load/Store    2            2 
32k/32k L1 cache           ? small             32/32?        32/32
256k on chip L2 cache        512k on chip      128MB+        512k
~1.34GB/sec bus bandwidth     4.2               10+?         6.4
no out of order exectution    OOOE             OOOE          OOOE
2MB L3 cache                  none             none           ?
Altivec (4 pipeline)     SSE/MMX(shared)       none        Altivec?
No x86 decode step          x86 decode         no             no
7 stage pipeline              20               10?            ?
Single core                  single            dual        single
dual-processor               single            multi        dual
.18 micron SOI                .13              .18         .13/.09 SOI

tidying up the fonts a bit.


The L2/L3 aspect of Power4 is wrong. The large cache is L3. but this doesn't matter too much at this level of examination. I doubt the .18 for Power4 as well. IBM threw all their best design/fab capabilities into Power4. Each of us could always go and read the many thousands of detailed words on IBMs site if we really wish to know though...

One approach IBm has is to use dies where only one CPU core is working. If this is the case, which GPUL strongly suggests isn't the case, then the numbers would stay the same apart from there only being one core.

But all the talk is of a new design. Reducing the L1 and L2 caches would reduce the area of the die, improving the yield. For Power4, yield is virtually irrelevant. For a lower end CPU, yield is massively important. So the cache sizes are likely to be reduced (L3 is inherently off-chip on Power4 and will probably stay that way). Being able to retire 8 instructions per cycle is probably overkill - something like 6 sounds more likely. Maybe one less INT/FP unit? Die yield will also be increased with .13 or .09, so this seems very plausible - remember the 0.09 fab IBM just built near Fishkill recently? I imagine there will also be a cheaper version with only one CPU core - possibly achieved by re-using the dies where the second core did not work. 6.4GB of memory bandwidth is great if you can manage it, but if commodity DRAM parts won't let this be achieved, this will be simplified as well to make it cheaper.

That's probably at least 5 cents worth.
 
Increasing Mhz on the Intel side

Well, to be very frank Apple is always going to be trailing in the Mhz figures ( comparing to Intel and AMD). Intels are like Lira (Italian Currency) and the G4 like the US Dollar. Having more Lira's doesn't mean that the person is rich, all that counts is performance. G4's are a better architecture compared to the P4's, if we have the Altivec (aka Velocity Engine) , to counter us the PC's have the increasing number of Pipeline stages.

Well as for the the performance of apps/games on OS X is concerend most of the them have been written with a pc architecture in mind and then are ported to mac. No developer is going to re-write the whole code. Hence, we see the macs not performing well when it comes to pc ported apps and games. Do not blame Apple for that it's the developers fault. Or else how can a mac be 50 times faster than a PC(pentium 4) on a Program like Blast. In short, ported codes bad, native apps written/re-written from scratch good.
 
Re: photon processor

Originally posted by macmax
did you hear about this?
in 4 or5 years it is supposed to be working.
it will work in tetrabytes .it will work in a computer with no hard drive , but a protein cube.
it is an effort of apple and ibm.
Click to expand...

scotty, beam me up...:D
yes, I like science fiction, too.
 
Just to correct some things. The POWER4 has 96 kB of L1 cache per processor (64 instruction/32 Data), 32 MB of shared L3 cache per chip and 1.5 MB of L2 cache (3 lots of 512 kB) per chip.

The L2 cache takes up around half the transistor count of the POWER4 if you are wondering.

The POWER4 is produced on 0.18µm SOI process and will be released on a 0.13µm SOI process in late October/Early November.

The POWER4 can only dispatch 1 group of instructions per cycle, which is 5 instructions. It can fetch 8 per cycle though. That isn't going to change in the chip announced October 15. Too much effort and why you would bother I have no idea.

The memory interface can deliver ~11GB/s and since it runs through the L3 cache if they intend to keep the same system the new chip will have L3 cache. I/O bandwidth is considerably lower though.

If I missed anything someone wants just say and I will add it.

the question mark next to Altivec isn't about whether the GPUL will have it, it's about whether it will share execution units like the P4, or have seperate ones like the G4.
Click to expand...
Given it wasn't until IBM saw Altivec that they saw the worth in a SIMD unit I'd be expecting separate.

Edit: A sentence was annoying me and I couldn't be bothered fixing it.
 
Originally posted by Telomar

The L2 cache takes up around half the transistor count of the POWER4 if you are wondering. Not quite but it takes up a substantial amount.
Click to expand...

That L2 takes quite so much die space I hadn't reallised. Making L2 and L3 smaller seems to be a sensible way to go then.

The web site seems a little contradictory on the L3 size - one table says L3 can be 32Mb, 64MB or 128MB whereas the bulk of the text addresses only a 32Mb L3 cache. I guess this is a difference between what IBM is actually building versus the design capabilities.

I hope there's some detailed info on GPUL (or whatever!) after the MPR presentation - it took ages to get a really detailed desciption of Power4 on line.

And as a silly aside - I think I met one the the Power4 designers in the Rabbit Ridge vineyard in CA a few years ago. Zinfandel was the subject though!
 
Originally posted by nixd2001
That L2 takes quite so much die space
Click to expand...

Hmm. transistor count isn't necessarily the same as die area. Any comments on how these two relate, Telomar?
 
nixd2001:

Die space is a funtion of both transistor count and interconnect space. (Where "internconnect space" is a function of distance of points to connect as well as how many points to connect.)

Cache is typically denser in transistors than other areas of the chip because of less complicated interconnection, but big caches require a lot of transistors and still take up a lot of die space.
 
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