Note that IBM/Apple needs to double the amount of memory bandwidth per chip in order to maintain performance.
If the dual-core chips shares one memory bus (for example, if the dual-core chip (or 2) are dropped into the current G5 architecture) then the memory bandwidth *per CPU* will be halved.
That's gotta hurt.
They'll need to double the speed of the bus, double the number of busses, or double the width of the bus to maintain the current balance of memory bandwidth per CPU.