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Re: Re: Re: lots of new supercomputers
As far as Floating Point goes, Altivec in its current form can only work on 4 32bit-Floats/single precision (with Integer there's also the option of 8*16bit and 16*8bit! The Integer-part of Floats is usually 15bit from what i know, hence 16bit or 8bit floats wouldn't really make sense! ;-), also on the G5 since the G5s "VMX" is more or less just the Altivec-Unit they made back in the day together with Moto in Somerset for the 7400-G4, and they just seem to have dug out their old masks and layouts! ;-)
They could add the option of 2*64bit in a later Altivec-Revision, but that's not that much SIMD (Single Instruction MULTIPLE Data) anymore, is it? ;-) Would still be nice, as you could crunch twice the 64bit-Numbers compared to today (4 instead of 2 at a time!)!
And an extension from 128bit to 256bit would be quite an undertaking! Altivec-Units already generally take up quite a bit of Die-Space!
There have been rumours about an extended Version of Altivec for some time, but nothing definate has emerged! It seems though that since the P970 was made IBM does have an interest in Altivec and developing it finally! I wouldn't count on Motorola anymore to do the job!
Point is: Quite a few compute-intensive jobs can work with 32bit-Floats, just look at the NASA's Jet3D or Genentech's BLAST gene sequencing!
And no, SSE2 is *not* any better "since it can do 64bit double precision", because in a P4 you can either use SSE2 *or* the really weak single-precision 32bit-FPU, not both at the same time, since it's basically the same Unit! ;-) With the Athlon and Opteron, they just "map" SSE(2) commands onto the regular FPUs internally, hence they just fare "okay" in that!
With the G4 and G5, the 64bit-FPU(s) and Altivec *can* run in parallel if properly scheduled, and i sure hope IBMs XLC does a good job in scheduling appropriately! ;-)
What's more is that the G4s and G5s FPUs are naturally Double Precision 64bit (and have been since 60x-times!), a P4 and Athlon/Opteron either have to emulate it using the 32bit-FPU working on 2 32bit-Floats (huge performance-hit!) or have to use SSE2 for it!
So the G5s FPUs on their own already are very powerful and competitive to Systems ALREADY using the SSE2-SIMD-Extension, and Altivec is for the moment just a VERY nice bonus, that can later on be pretty nicely used for certain Tasks! 🙂
This is for the Virginia Tech People on here: GET CRAIG HUNTER FROM THE NASA IF YOU WANT TO DO FLUID DYNAMICS AND SEE THAT THING FLY USING ALTIVEC! ;-)
P.S.: Altivec seems to work very well though for quad or octa-precision! Check out the PDF and Sample Code on Apple's Website!
As far as Floating Point goes, Altivec in its current form can only work on 4 32bit-Floats/single precision (with Integer there's also the option of 8*16bit and 16*8bit! The Integer-part of Floats is usually 15bit from what i know, hence 16bit or 8bit floats wouldn't really make sense! ;-), also on the G5 since the G5s "VMX" is more or less just the Altivec-Unit they made back in the day together with Moto in Somerset for the 7400-G4, and they just seem to have dug out their old masks and layouts! ;-)
They could add the option of 2*64bit in a later Altivec-Revision, but that's not that much SIMD (Single Instruction MULTIPLE Data) anymore, is it? ;-) Would still be nice, as you could crunch twice the 64bit-Numbers compared to today (4 instead of 2 at a time!)!
And an extension from 128bit to 256bit would be quite an undertaking! Altivec-Units already generally take up quite a bit of Die-Space!
There have been rumours about an extended Version of Altivec for some time, but nothing definate has emerged! It seems though that since the P970 was made IBM does have an interest in Altivec and developing it finally! I wouldn't count on Motorola anymore to do the job!
Point is: Quite a few compute-intensive jobs can work with 32bit-Floats, just look at the NASA's Jet3D or Genentech's BLAST gene sequencing!
And no, SSE2 is *not* any better "since it can do 64bit double precision", because in a P4 you can either use SSE2 *or* the really weak single-precision 32bit-FPU, not both at the same time, since it's basically the same Unit! ;-) With the Athlon and Opteron, they just "map" SSE(2) commands onto the regular FPUs internally, hence they just fare "okay" in that!
With the G4 and G5, the 64bit-FPU(s) and Altivec *can* run in parallel if properly scheduled, and i sure hope IBMs XLC does a good job in scheduling appropriately! ;-)
What's more is that the G4s and G5s FPUs are naturally Double Precision 64bit (and have been since 60x-times!), a P4 and Athlon/Opteron either have to emulate it using the 32bit-FPU working on 2 32bit-Floats (huge performance-hit!) or have to use SSE2 for it!
So the G5s FPUs on their own already are very powerful and competitive to Systems ALREADY using the SSE2-SIMD-Extension, and Altivec is for the moment just a VERY nice bonus, that can later on be pretty nicely used for certain Tasks! 🙂
This is for the Virginia Tech People on here: GET CRAIG HUNTER FROM THE NASA IF YOU WANT TO DO FLUID DYNAMICS AND SEE THAT THING FLY USING ALTIVEC! ;-)
P.S.: Altivec seems to work very well though for quad or octa-precision! Check out the PDF and Sample Code on Apple's Website!