MP 7,1 MP 7,1 PCIe lane bifurcation?

Slash-2CPU

macrumors 6502
Original poster
Dec 14, 2016
347
201
The ability to split a x16 slot into four x4 logical or split an x8 into two x4 is a common capability of modern Xeon WS/server boards. This is without the use of a PCIe bridge chip.

Has anyone tried using one of the bridge less bifurcation-supported dual or quad m.2 NVME boards in a 7,1?
 

deconstruct60

macrumors G3
Mar 10, 2009
8,492
1,475
Slot 4 - I have an Afterburner in 5 and the others are x8.
Slot 4 isn't really x16 unless in a relatively narrow corner case. ( zero Thunderbolt & USB 3.1 usage in whole system. ). it is x16 "electrical' but the bandwidth isn't necessarily x16 worth ( Pretty sure it is on "Pool B", but can't tweak it between pools. ) It is feed from a PCI-e switch so not 'straight from CPU' lanes assignment looking for. Slot 1 and Slot 3 are the only "clean from the CPU" slots. The rest ( including MPX connector's PCI-e portion and base system's TB controller feeds are all on a switch. ).
 

repoman27

macrumors 6502
May 13, 2011
435
77
Yeah, slots 2 and 4 are almost certainly not going to work due to the fact that they each share 8 lanes via muxes with the proprietary portion of the MPX slot below them.

The Broadcom PEX8796 PCIe switch in the Mac Pro is quite capable and can support up to 24 ports. It also has no problem with x4 lane width configurations. Whether or not you can get it to dynamically bifurcate without any available EFI settings is another matter.
 

Virtuoso

macrumors regular
Feb 21, 2008
152
14
Seattle
I'll be kicking myself if slot 3 works! I just got a Highpoint 7101A today because I thought the Asus was a no-go.
 

repoman27

macrumors 6502
May 13, 2011
435
77
Slot 4 isn't really x16 unless in a relatively narrow corner case. ( zero Thunderbolt & USB 3.1 usage in whole system. ). it is x16 "electrical' but the bandwidth isn't necessarily x16 worth ( Pretty sure it is on "Pool B", but can't tweak it between pools. ) It is feed from a PCI-e switch so not 'straight from CPU' lanes assignment looking for. Slot 1 and Slot 3 are the only "clean from the CPU" slots. The rest ( including MPX connector's PCI-e portion and base system's TB controller feeds are all on a switch. ).
Slot 4 is always x16 unless it's covered by a dual-slot MPX module. The utilization reported in the Expansion Slot Utility for the bandwidth allocation pools is a little misleading. As soon as you plug a device into any Thunderbolt bus it adds 25% to pool B, even if it's a device that doesn't use any PCIe bandwidth, simply because you've lit up a Thunderbolt controller with a PCIe Gen3 x4 host connection. There's a big difference between oversubscribing an upstream connection and changing the actual physical/electrical lane width of a PCIe link.