It’s important not to mix up two different things. TSMC’s SoIC (System on Integrated Chips) architecture is different from TSMC’s WMCM (Wafer-level Multi-Chip Module) packaging. They are not the same thing.That still doesn't mean it's faulty... It's a design decision to help improve yields because with McM you can have smaller die chunks tied together. If the same silicon process is used, there is no difference in errors per wafer in either case, It's just that with smaller chips that you piece together with McM you can get better yield from the wafer overall as one error takes out a smaller chunk. The end product you are using is not faulty just because other chips on the wafer are bad, or because one CPU is disabled on your chip because of an error on the wafer. This process has been used FOREVER in silicon design and is called binning. That's how you get so many different tiers of chips from one piece of silicon. That doesn't magically stop being the case once McM is used...
AMD has been doing MCM for a while now, and when you buy a 6 core vs an 8 core, the silicon on the chip is identical, but the 6 core has two cores disabled, likely due to errors in the silicon die. But the 6 cores you were sold are not faulty, just the two that were disabled. But you were sold 6 cores and got what you paid for so the chip isn't faulty.
There are two rumors, both are well-founded and likely to be accurate.
The first rumor is that Apple is using SoIC architecture for M5 Pro/Max/Ultra. AMD was the first to use this, but Apple will now do so for its larger silicon.
The second rumor is that Apple will use WMCM packaging for A20/M6. WMCM is the successor to InFO-PoP, see here for a good overview, and note that the logic die in the package (along with memory and I/O dies) can be SoC or SoIC: