PC and Mac 64 bit processor architecture

The G5 is very different from the Athlon 64 in many ways. First, how the Athlon is better than the PowerPC: the Athlon has an integrated memory controller (which reduces time to access memory); the G5 doesn't have this feature (yet - IBM's planning on including it in a future revision, so I've heard). The Athlon also has a fully HyperTransport-enabled system bus, allowing it to run at 1600 MHz. The G5's system bus is also HyperTransport-enabled, but isn't quite as fast (800 MHz to 1000 MHz). The Athlon also has a large cache (128KB L1 and 1024KB L2) compared to the G5's (64KB L1 and 512KB L2). Now for the advantages of the PowerPC G5: The G5 is RISC-based, and thus does not have as many instructions to manage as a CISC design - meaning more instructions get executed in the same amount of time. The Athlon 64 is even more weighted down than other x86-based processors due to the additional instructions for supporting 64 bits; that load is reduced from what it would otherwise be since some of the older parts of x86 were removed from this processor - but it is still FAR higher than that of the G5. Unlike most other processors, the PowerPC G5 has the ability to have a long pipeline and have over 200 instructions in various states of execution all at once. The Athlon is a traditional long pipeline design, which means it can scale well, but has a much lower instructions-in-process count (less work gets done in the same amount of time). The G5's biggest advantage is the Altivec unit - vector operations show how the G5 can fly; the built-in floating-point unit can also work in concert with it. The Athlon is still stuck with the weak floating-point unit, plus a vector unit that has to do all the work otherwise done by the floating-point unit, limiting performance.

 

Well I think that sums it up for me

 

Not sure what you are on about, Athlon 64 only has about 12 or 14 stages in the pipeline. As a comparison, prescott has 31 stages. Thats why Intel scale well and can get 3Ghz+. AMD has been RISC based for ages. They use x86 decoders to convert the instructions. Obviously having to decode instructions hasn't been an impediment for performance if they are competitive with Intel. Having a long pipeline is also not necessarily an advantage. If you get the branch prediction wrong and have to flush the pipeline, you take a bigger performance hit for having a long pipeline.

There is also no penalty for the AMD in being 64bit. Actually the AMD does 64bit and 32bit code at the same time better than the G5. It does not require a 32bit-64bit bridge like the G5 does. There are no "older parts x86 removed" in the AMD, if they did that it wouldn't be x86 compatible.

Also, when you are referring to the G5 800-1000Mhz bus, thats the FSB. The FSB of the G5 is not HT. In a G5 system, the HT bus connects the system controller to the other I/O subsystems. An Athlon 64, strictly speaking, does not have a FSB since the memory controller is built into the CPU.

Also, the HT both architectures support is the same 800Mhz 16 bit bidirectional one.

Finally, AMD are renowned for having the strongest FPU performance. If you deactivated AltiVec, MMX, SSE or any of those other special instruction sets, you'd find the AMD easily on top.

 

Thank you for clearing that up! I'm now better informed regarding AMD processors.

 

The FSB on the PPC970 is NOT Hypertransport, it's a mix of the 4 different busses used on the Power4. FS Bus is called ApplePI, Elastic Bus.

HyperTransport in the G5 is used purely as a I/O interconnect between chips on the G5.

The only "real" hypertransport componenet is probably the AMD PCI/PCI-X style HT Tunnel.

System Controller <--HT--> PCI/PCI-X HT Tunnel <--HT--> KeyLargo2 I/O

Apple really hasn't said what the System controller is... but it's most likely not HT inside, just a HT port to I/O.

Note: The KeyLargo2 uses PCI interconnects to string the I/O components together.

 

Opteron vs G5

few questions about the G5 architecture.
-G5's are native RISC so they would "need" one less pipeline stage (decode) and still be able to scale as quickly as an X86 processor correct?
-Does the G5 have a classic frontside bus and north bridge?
-If it does have a north bridge and FSB what is the clock speed and width of it?
-how many pipeline stages does the G5 have?
-if the G5 is based on the Power4 architecture, does it share the same instruction set?
-do G5 boards have a 128 bit or 64 bit memory controller?
-how many execution units (ALU, FPU) does the G5 have?

 

If only we could get a PPC970 core in an Opteron's body. Clearly AMD has a far superior memory system, and it seems IBM has a more powerful, more efficient core.

jbraun:

The x86 chips need at least one more stage for decode. Though the G5 actually breaks down a couple PPC instructions in a similar fassion to the x86 chips.

Pretty much.

FSB has thus far been two 32-bit unidirectional busses at half the G5's core clock. Although high bandwidth, this setup is almost certainly higher latency than more traditional setups like what a P4 has.

A bit like the P4, but not as many.

Not quite. The G5 has AltiVec, the Power4 might have a few specialized instructions, you'd need to look into that more.

128 bit.

Quite a few, most notably two floating point units and two integer units. See:

http://arstechnica.com/wankerdesk/3q02/powerpc.html
http://arstechnica.com/cpu/02q2/ppc970/ppc970-1.html