Originally posted by Catfish_Man
In reply to a few of the posts here:
The 970 is single core without hyperthreading (or symmetric multithreading to be more accurate, hyperthreading is Intel's name for SMT). When the 970 goes to a .09 micron manufacturing process, dual core may become practical (.13 ->.09 cuts the transistor size in half) A POWER5 derivative seems fairly likely, and would have hyperthreading. The 4x performance boost from ht is widely regarded as bull**** marketing claims, but it should give a fairly good boost (especially if the POWER4 isn't using its execution resources effectively. The Alpha EV8 was going to get a huge boost because it had way more execution units than it could normally use, and ht allowed it to use them more effectively). Neither the POWER4 nor the POWER5 will be used in Macs (the POWER4 costs several thousand dollars per chip, I've heard $7000-$8000). The 970 seems almost certain to be used in Macs (targetted at the desktop, has Altivec, etc...).
Just FYI, Hyperthreading is Simultaneous Multithreading, not symetric multithreading. I believe you were mixing up the term with symetric multiprocessing (what the dual processors do)
Also, the Intel Xenon chip is actually a P4 processor with unique features not added to the regular P4. Hyperthreading was one of these, but now the P4 utilizes this, so there is one less reason to get a Xenon processor.
Simultaneous Multithreading (hyperthreading) is both a good thing and a bad thing. Tests done with the Xenon differ greatly in performance with SMT turnned on and off. The problem with SMT is that sometimes one of the two programs being processed consumes too much of the cache resources. Then, the other program is starved of resources. The Xenon/P4 chips only put limits on the processor's execution resources, not memory resources. Therefore, a process can only use up half of the processor's queue slots, but all of the memory registers. Thus, one process has nothing in the cache and can't fill the other execution slots (which is the advantage of SMT). B/c the operating system thinks of them as two processors, it doesn't budget the "time-slicing". "Time-slicing" gives a process so many cycles of the processor's undivided attention and memory resources and then removes all of it from the processor's memory registers and puts it into a higher level of memory, and then brings in the next process, which has undivided attention etc. With the SMT, though, the OS thinks that, since there are two processors, each processor must have its own resources. The processor isn't designed to budget the memory resources, and one process, although constantly looking through the memory registers for its next part to process, never recieves anything to process b/c the other is a hog.
Another thing, someone posted that programs would have to be rewritten to take advantage of SMT. Yes and No. The only reason a program would have to be written to take advantage of SMT is if it is wanting to process two of its own threads simultaneously. The WinXP OS is designed to Hyperthread two applications. Applications would have to be written if they want to Hyperthread themselves.
Long story short, unless a hyperthreaded Power4 derivative is designed to budget all resources, there will be the same short commings as the Xenon/P4.
Also, someone earlier posted that the 970 and Power5 have not been produced. That is a false statement. The 970 is already being prepared for distribution. The Power5 has been produced and already been used in a test machine. That isn't to say it is complete, but it has been produced and is being tested to work bugs out of it.
That is my 50cents worth (or whatever value you think what I had to say has). For more info on Hyperthreading, go to
http://arstechnica.com/paedia/h/hyperthreading/hyperthreading-1.html , although I do not know if everyone will be able to comprehend what is said. Ars Technica is a valuable resource for people wanting to learn how processors work from simple explanations to complex ones.
