With all this talk of Apple moving to 970's across the board I have begin to think that this may actually be a possibility. Now I am not getting my hopes up, but maybe our man Jobs would try extremely hard to do this just to spit in the face of motorola, not that they would care all that much. I am in favor of putting the G4 in the ibook and I dont have a problem with it in the imac, but to be able to finally be free of motorola would be like a dream come true.
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PowerPC 970 up to 2.5GHz?
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Re: about the bus speed
Bus speeds are always based on integer or half integer multiples of the CPU clock speed. If you look at the bus speeds on various models you will find this to be true (e.g. PBG4 1Ghz/133=8x, 1Ghz/166=6x, PMG4 1.42/166=8.5, 1.25/166=7.5). The nice thing about the 970 is that it supports a bus multiplier as low as 2x at the speeds its given (a rarity these days...). I would presume that it additional supports half integers from 2.5x-8x (putting the 1.8Ghz part on busses from 225-900 Mhz DDR busses).
What does this mean to the motherboard manufacturer? Well, for one thing it means that Apple will probably have build a MB with a 200Mhz main bus, a 400Mhz memory bus (200DDR), and the northbridge with a 900DDR/32-bit to 400DDR/64-bit converter. AFAIK the fastest DDR chips are currently the DDR400/PC-3200 chips. These would interface nicely with the PPC970 1.8Ghz part on the 2x bus. But higher clocked chips would need to use higher multipliers. Like the 2.5Ghz part that sparked this whole discussion, would have a 1.25Ghz bus when running in 2x mode - nearly 8.9GB/s bandwidth, but requiring DDR550/PC-4400 RAM to satisfy that massive appetite. But if you put it in 3x mode, then it would run an 833Mhz bus, which is satisfiable with DDR400/PC-3200.
This is hell for motherboard makers, and especially Apple, becuase they can't make things that are fullbore all the time. DDR550 doesn't even exist yet AFAIK, so you couldn't even make the 2.5Ghz part run at 2x multiplier. But heck, we've been stuck at 5x+ multipliers for a long time, so getting down to 2x again will be real nice - the 970 will scream!
Bus speeds are always based on integer or half integer multiples of the CPU clock speed. If you look at the bus speeds on various models you will find this to be true (e.g. PBG4 1Ghz/133=8x, 1Ghz/166=6x, PMG4 1.42/166=8.5, 1.25/166=7.5). The nice thing about the 970 is that it supports a bus multiplier as low as 2x at the speeds its given (a rarity these days...). I would presume that it additional supports half integers from 2.5x-8x (putting the 1.8Ghz part on busses from 225-900 Mhz DDR busses).
What does this mean to the motherboard manufacturer? Well, for one thing it means that Apple will probably have build a MB with a 200Mhz main bus, a 400Mhz memory bus (200DDR), and the northbridge with a 900DDR/32-bit to 400DDR/64-bit converter. AFAIK the fastest DDR chips are currently the DDR400/PC-3200 chips. These would interface nicely with the PPC970 1.8Ghz part on the 2x bus. But higher clocked chips would need to use higher multipliers. Like the 2.5Ghz part that sparked this whole discussion, would have a 1.25Ghz bus when running in 2x mode - nearly 8.9GB/s bandwidth, but requiring DDR550/PC-4400 RAM to satisfy that massive appetite. But if you put it in 3x mode, then it would run an 833Mhz bus, which is satisfiable with DDR400/PC-3200.
This is hell for motherboard makers, and especially Apple, becuase they can't make things that are fullbore all the time. DDR550 doesn't even exist yet AFAIK, so you couldn't even make the 2.5Ghz part run at 2x multiplier. But heck, we've been stuck at 5x+ multipliers for a long time, so getting down to 2x again will be real nice - the 970 will scream!
Re: Re: about the bus speed
That's some very insightful commentary. Thank you for enlightening me a bit more today.
I've heard rumors to the tune of DDR 400 motherboards in "alpha" stage right now with the 970's. I think it makes sense that Apple will try to get the buses to a bandwith that won't neuter the 970's cahones... but I agree that it won't always be an ideal 2:1 ratio. It just doesn't make sense from a manufacturing standpoint. You're points on the current ratios make this very clear to me.
That's some very insightful commentary. Thank you for enlightening me a bit more today.
I've heard rumors to the tune of DDR 400 motherboards in "alpha" stage right now with the 970's. I think it makes sense that Apple will try to get the buses to a bandwith that won't neuter the 970's cahones... but I agree that it won't always be an ideal 2:1 ratio. It just doesn't make sense from a manufacturing standpoint. You're points on the current ratios make this very clear to me.
Re: about the bus speed
Yes, this proves (although the simple fact that the CPU is running at 1.8GHz and the FSB at 900MHz makes such arithmetically obvious) that the CPU:FSB clock multiplier is 2. HOWEVER, that does NOT mean that that multiplier is fixed at 2.0 for all speed bumps of the processor!
Example: the 2.8GHz P4 has an FSB of 533 MHz, yielding a CPU:FSB ratio of 5.25 (21/4). However, the 3.06GHz P4 ALSO has an FSB of 533MHz, yeilding a ratio of 5.75 (23/4). Intel plans on putting an 800MHz FSB on the 3.2 GHz P4/P5 if I recall correctly, which would yield a 4.0 CPU:FSB ratio.
In fact, the CPU:FSB ratio hasn't been fixed across speed-bumps on any Intel CPU since the 486 (remember "DX/2"? That was when Intel made the CPU:FSB ratio fixed at 2.0 instead of 1.0!) On Moto/IBM chips, I'm not sure when the last fixed-ratio line of chips was put out, but I imagine it was quite a while back.
You see, if your FSB changes with every speed bump on the CPU, then you have to engineer that change into the System Controller (or North Bridge, depending on which architecture you're talking about) chip. Back in the bad old days of fixed ratios, moving from a slower chip to a faster chip - an occurence we take largely for granted these days - meant throwing out or fire-saling the old motherboards (the CPUs were soldered on anyways), designing or augmenting the silicon design of your chipset north bridge, and potentially redesigning your motherboard. Because of the changes required to support a speed bump, often they weren't all done correctly, and motherboards shipped with either the CPUs or the peripheral ISA connectors clocked at the wrong speed.
That paradigm is wasteful, error-prone, and expensive for everyone but the CPU manufacturer. It also forces the CPU manufacturer to not ship minor speed bumps, but rather concentrate on much more substantial "bumps" much less often (ie, 386-16, 386-20 (+25%), 386-25 (+20%) ... much wider differences there than 2.6GHz, 2.8GHz (+7.7%), 3.06 (+9.3%)), and still have major OEM-relations projects that ended up costing the CPU manufacturer money and resources to offset the costs to their OEMs.
Now, given that the 1.8GHz 970 has an FSB of 900 MHz, it is patently obvious that the CPU:FSB ratio on that particular part is shipped at 2.0. However, given the 970 press release which gives a range of CPU speeds (1.8-2.5GHz) and a single FSB speed (800MHz effective, which we know from other documentation is 900MHz - overhead), I do not see any reason to conclude that the 2.5GHz part will have a 1.25GHz FSB.
In fact, to do so would cause both IBM and Apple massive re-engineering headaches and be, to be quite frank, absolutely stupid.
The only bit I can see above which might lead one to believe that the 970 has a 2:1 CPU:FSB ratio is David Wang's aside:
If it is set at a single integer ratio (Intel uses two integers, allowing for non-integral overall ratios like 21/4) then the 2.5GHz chip would have to use either 2.0 (yielding the awkward 1.25GHz FSB) or 3.0 (yielding the even more awkward 833MHz FSB). In fact, given an integral constraint, I would have expected the "next" speed bump to be at 2.7GHz, retaining the 900MHz FSB, albeit with a massive performance difference between consecutive speed-bump chips (I am assuming that with the 1.8-2.5GHz range advertised IBM is planning on having a few speed steps between the two extremes to allow buyers flexibility).
I suppose, if this is really true (single-integer ratios) then given that reality an FSB of 1.25GHz would certainly be preferable to a "downgraded" 833MHz FSB from the consumer perspective, but would require something just short of a bona-fide miracle on the interconnect side of things to get a motherboard using this higher-frequency chip out the door. Note that with CPU frequency ramp-up escalating in general far more steeply than inter-processor interconnect frequencies, you'll very soon have to do one of the following:
1) Release a speed bump CPU with a slower FSB (say, the 2.7GHz chip with 900MHz FSB), which would quite likely make the "faster" chip perform worse than the ostensibly cheaper "slower" chip.
2) Introduce a "massive" speed bump in CPU frequency while keeping the FSB constant (2.5GHz->3.75GHz!). While consumers would "love" this, remember that this is incredibly wasteful from a CPU manufacturing standpoint, as for every, say 100 3.75GHz CPUs you might be producing 1000 CPUs that would have functioned quite well at 3.0GHz, and had you implemented a more reasonable dual-integer multiplier strategy you would have been able to sell those chips for much more than you're able to sell them rated at only 2.5GHz, or you will have to up the multiplier to 3 on those 3.0GHz chips, have a slower 1GHz FSB, and still sell them for about what the 2.5GHz chips are selling, given that overall end-user performance would probably even out if not be a bit worse. Can you imagine Intel not having produced any chips between 2.0GHz and 3.0GHz? Intel's market share certainly would not be where it is today had Intel used such an approach!
3) Force your OEMs (Apple and IBM now, but IBM wants others too) to perform chipset miracles heretofore unseen in the computing industry.
Given these highly-unsatisfactory options, I am inclined to believe that David Wang either mispoke or is somehow misinformed. IBM's too smart to stick with a design limitation that's been overcome cheaply and easily for over 10 years.
Yes, this proves (although the simple fact that the CPU is running at 1.8GHz and the FSB at 900MHz makes such arithmetically obvious) that the CPU:FSB clock multiplier is 2. HOWEVER, that does NOT mean that that multiplier is fixed at 2.0 for all speed bumps of the processor!
Example: the 2.8GHz P4 has an FSB of 533 MHz, yielding a CPU:FSB ratio of 5.25 (21/4). However, the 3.06GHz P4 ALSO has an FSB of 533MHz, yeilding a ratio of 5.75 (23/4). Intel plans on putting an 800MHz FSB on the 3.2 GHz P4/P5 if I recall correctly, which would yield a 4.0 CPU:FSB ratio.
In fact, the CPU:FSB ratio hasn't been fixed across speed-bumps on any Intel CPU since the 486 (remember "DX/2"? That was when Intel made the CPU:FSB ratio fixed at 2.0 instead of 1.0!) On Moto/IBM chips, I'm not sure when the last fixed-ratio line of chips was put out, but I imagine it was quite a while back.
You see, if your FSB changes with every speed bump on the CPU, then you have to engineer that change into the System Controller (or North Bridge, depending on which architecture you're talking about) chip. Back in the bad old days of fixed ratios, moving from a slower chip to a faster chip - an occurence we take largely for granted these days - meant throwing out or fire-saling the old motherboards (the CPUs were soldered on anyways), designing or augmenting the silicon design of your chipset north bridge, and potentially redesigning your motherboard. Because of the changes required to support a speed bump, often they weren't all done correctly, and motherboards shipped with either the CPUs or the peripheral ISA connectors clocked at the wrong speed.
That paradigm is wasteful, error-prone, and expensive for everyone but the CPU manufacturer. It also forces the CPU manufacturer to not ship minor speed bumps, but rather concentrate on much more substantial "bumps" much less often (ie, 386-16, 386-20 (+25%), 386-25 (+20%) ... much wider differences there than 2.6GHz, 2.8GHz (+7.7%), 3.06 (+9.3%)), and still have major OEM-relations projects that ended up costing the CPU manufacturer money and resources to offset the costs to their OEMs.
Now, given that the 1.8GHz 970 has an FSB of 900 MHz, it is patently obvious that the CPU:FSB ratio on that particular part is shipped at 2.0. However, given the 970 press release which gives a range of CPU speeds (1.8-2.5GHz) and a single FSB speed (800MHz effective, which we know from other documentation is 900MHz - overhead), I do not see any reason to conclude that the 2.5GHz part will have a 1.25GHz FSB.
In fact, to do so would cause both IBM and Apple massive re-engineering headaches and be, to be quite frank, absolutely stupid.
The only bit I can see above which might lead one to believe that the 970 has a 2:1 CPU:FSB ratio is David Wang's aside:
If it is set at a single integer ratio (Intel uses two integers, allowing for non-integral overall ratios like 21/4) then the 2.5GHz chip would have to use either 2.0 (yielding the awkward 1.25GHz FSB) or 3.0 (yielding the even more awkward 833MHz FSB). In fact, given an integral constraint, I would have expected the "next" speed bump to be at 2.7GHz, retaining the 900MHz FSB, albeit with a massive performance difference between consecutive speed-bump chips (I am assuming that with the 1.8-2.5GHz range advertised IBM is planning on having a few speed steps between the two extremes to allow buyers flexibility).
I suppose, if this is really true (single-integer ratios) then given that reality an FSB of 1.25GHz would certainly be preferable to a "downgraded" 833MHz FSB from the consumer perspective, but would require something just short of a bona-fide miracle on the interconnect side of things to get a motherboard using this higher-frequency chip out the door. Note that with CPU frequency ramp-up escalating in general far more steeply than inter-processor interconnect frequencies, you'll very soon have to do one of the following:
1) Release a speed bump CPU with a slower FSB (say, the 2.7GHz chip with 900MHz FSB), which would quite likely make the "faster" chip perform worse than the ostensibly cheaper "slower" chip.
2) Introduce a "massive" speed bump in CPU frequency while keeping the FSB constant (2.5GHz->3.75GHz!). While consumers would "love" this, remember that this is incredibly wasteful from a CPU manufacturing standpoint, as for every, say 100 3.75GHz CPUs you might be producing 1000 CPUs that would have functioned quite well at 3.0GHz, and had you implemented a more reasonable dual-integer multiplier strategy you would have been able to sell those chips for much more than you're able to sell them rated at only 2.5GHz, or you will have to up the multiplier to 3 on those 3.0GHz chips, have a slower 1GHz FSB, and still sell them for about what the 2.5GHz chips are selling, given that overall end-user performance would probably even out if not be a bit worse. Can you imagine Intel not having produced any chips between 2.0GHz and 3.0GHz? Intel's market share certainly would not be where it is today had Intel used such an approach!
3) Force your OEMs (Apple and IBM now, but IBM wants others too) to perform chipset miracles heretofore unseen in the computing industry.
Given these highly-unsatisfactory options, I am inclined to believe that David Wang either mispoke or is somehow misinformed. IBM's too smart to stick with a design limitation that's been overcome cheaply and easily for over 10 years.
beowolf:
Ah, you have the right quote there, you just misread a bit of it. Arstech said:
Put another way, a chip with a multiplyer of 8x has the FSB running at 1/8th of core speed, and 9x means 1/9th. So Apple can do exactly what is normal: set the FSB to something they like and then just set the multiplier. Lets assume that Apple chooses 600mhz for their FSB. Since the base clock is 300mhz, this means that any multiple of 300mhz is a valid CPU clock speed, so Apple could go ahead and release 1.8ghz, 1.5ghz, and 1.2ghz PPC-970 machines.
Rincewind42:
You seem to be assuming that the PPC-970 does multipliers just like all other processors, which may not be the case.
Frobozz:
There is no evidence that I know of suggesting that the PPC-970 supports half-integer multipliers as most chips do, and there is no reason that Apple can't adjust their FSB's in 1mhz increments if they want. Overclockers do it all the time, and have for years.
Ah, you have the right quote there, you just misread a bit of it. Arstech said:
Note that the possiblity of other integer fractions is quite open, so what we have here is just about exactly like what conventional processors do, except that apparently half-FSB multiples are not supported.
Put another way, a chip with a multiplyer of 8x has the FSB running at 1/8th of core speed, and 9x means 1/9th. So Apple can do exactly what is normal: set the FSB to something they like and then just set the multiplier. Lets assume that Apple chooses 600mhz for their FSB. Since the base clock is 300mhz, this means that any multiple of 300mhz is a valid CPU clock speed, so Apple could go ahead and release 1.8ghz, 1.5ghz, and 1.2ghz PPC-970 machines.
Actually there are quite a number of PC chipsets (and mobos based on them) that can run the FSB out of synch with the other busses. A system controller could be made for a PPC-970 that supports essentially any FSB, although that sort of flexability leads to higher memory access latency (bad).
Rincewind42:
You seem to be assuming that the PPC-970 does multipliers just like all other processors, which may not be the case.
Hell or not, you'd be hard pressed to find a PC chipset that doesn't support asyncronous FSB and memory operation (well, the VIA KT133A didn't, nor did the AMD 750, 760, or 760MP, as far as I know).
Frobozz:
Insightful, but also not quite right.
There is no evidence that I know of suggesting that the PPC-970 supports half-integer multipliers as most chips do, and there is no reason that Apple can't adjust their FSB's in 1mhz increments if they want. Overclockers do it all the time, and have for years.Re: Re: about the bus speed
While this is historically true on the G4s (as far back as I can remember, at least!), it is not necessarily true on a new processor design. Intel chips, for instance use two integers (x and y) so that the overall CPU:FSB ratio can always be expressed as x/y (albeit with some restrictions on 'y' ... always 2 or 4 as far as I remember). After you take the DDR/QDR pumping of the FSB into account, the CPU:RawFSB is set at integral amounts, but I believe the 'y' factor can always be 'upped' should the need arise (ref: 650/750/850MHz P3s on a 100MHz FSB ... I believe but can not prove that the P4 retains this flexibility).
If IBM ever moves to quad-pumping their FSB, then I see no reason why we couldn't see 2.25, 2.5, 2.75, 3.0 CPU:FSB ratios, even without the tricks Moto uses to get half-step ratios on the G4. Given that IBM is currently double-pumping, then we should be able to see 2.0, 2.5, 3.0 ratios without any other tricks, or 2.25, 2.5, 2.75, 3.0 if IBM gets a bit fancier. All this with an integral CPU:RawFSB ratio.
While this is historically true on the G4s (as far back as I can remember, at least!), it is not necessarily true on a new processor design. Intel chips, for instance use two integers (x and y) so that the overall CPU:FSB ratio can always be expressed as x/y (albeit with some restrictions on 'y' ... always 2 or 4 as far as I remember). After you take the DDR/QDR pumping of the FSB into account, the CPU:RawFSB is set at integral amounts, but I believe the 'y' factor can always be 'upped' should the need arise (ref: 650/750/850MHz P3s on a 100MHz FSB ... I believe but can not prove that the P4 retains this flexibility).
If IBM ever moves to quad-pumping their FSB, then I see no reason why we couldn't see 2.25, 2.5, 2.75, 3.0 CPU:FSB ratios, even without the tricks Moto uses to get half-step ratios on the G4. Given that IBM is currently double-pumping, then we should be able to see 2.0, 2.5, 3.0 ratios without any other tricks, or 2.25, 2.5, 2.75, 3.0 if IBM gets a bit fancier. All this with an integral CPU:RawFSB ratio.
jettredmont:
I think that you're making things needlessly complex. Multipliers are not based on the effective clock speed of the FSB, they are based on the base clock speed. I see no reason to use two integers to represent the multiplier of a P4 since it's core clock speed can easily be expressed as an integer multiple of the base FSB clock speed.
I think that you're making things needlessly complex. Multipliers are not based on the effective clock speed of the FSB, they are based on the base clock speed. I see no reason to use two integers to represent the multiplier of a P4 since it's core clock speed can easily be expressed as an integer multiple of the base FSB clock speed.
more POWER poop
and buss speed info..
IBM is developing the "Fast Path" Architecture
which a Sun wag says is 'typical of IBM..to put
more software into the chip'..check out:
http://news.com/com/2100-1001-892774.html
and includes speculation on POWER6 and POWER7 architectures. YES they are being flexible in case they need either Infiniband, Rapid IO or
other high speed topologies. Apple might announce
"developer boards" in June/July..products in November..with a prior 'honorable mention to 64 bit people' at the May conference. That may still mean 2-2.5 GHz 970 chips in November-December..for
Christmas. TransMeta has already claimed "teraops" for some applications of the TM8000.
<---wants a 7557 with a "970 inside"
and buss speed info..
IBM is developing the "Fast Path" Architecture
which a Sun wag says is 'typical of IBM..to put
more software into the chip'..check out:
http://news.com/com/2100-1001-892774.html
and includes speculation on POWER6 and POWER7 architectures. YES they are being flexible in case they need either Infiniband, Rapid IO or
other high speed topologies. Apple might announce
"developer boards" in June/July..products in November..with a prior 'honorable mention to 64 bit people' at the May conference. That may still mean 2-2.5 GHz 970 chips in November-December..for
Christmas. TransMeta has already claimed "teraops" for some applications of the TM8000.
<---wants a 7557 with a "970 inside"
wms121:
It seems that it is safe to forget the 2.5ghz PPC-970 by Xmas:
http://news.zdnet.co.uk/story/0,,t269-s2131244,00.html
It seems that it is safe to forget the 2.5ghz PPC-970 by Xmas:
http://news.zdnet.co.uk/story/0,,t269-s2131244,00.html
ok..fixed the link
link:
http://news.com.com/2100-1001-892774.html
Hmm..also a 2.3 Teraflops chips could also mimic
32 Giganeurons/sec {64 bit processor emulator per neuron..not 64 bit weighted neural network}.
Thats one ten thousandth the capacity of the human
brain.
"Closer..closer..Will Robinson.."
link:
http://news.com.com/2100-1001-892774.html
Hmm..also a 2.3 Teraflops chips could also mimic
32 Giganeurons/sec {64 bit processor emulator per neuron..not 64 bit weighted neural network}.
Thats one ten thousandth the capacity of the human
brain.
"Closer..closer..Will Robinson.."
PowerMac coat tails
I'm not exactly sure what exactly 'market share' refers to, but Fred Anderson is also quoted as saying he'd like to get to $8 bil. in revenues, from $5.7 bil currently. For sure they'd need an increase across the entire line to get another $2.3 in revenues, but keep in mind that PowerMacs are big-ticket items. And there is a lot of pent-up demand for PowerMacs right now.
People who buy PowerMacs are also the people who buy the expensive displays, various hardware upgrades, and expensive pro software. So for each PowerMac they sell, they're probably making $3500-4000 in revenues. If they sold 500,000 more PowerMacs this year (which to me could very well happen if they bring out the 970 in the 1.8-2.0 range), they would get pretty close to the $2.3 bil in added revenues they're looking for. The XServes will also get a huge boost in sales if they came with the 970s.
If I knew that the 970 was a sure sure thing, I'd be investing a lot of money in Apple stock right now...
I'm not exactly sure what exactly 'market share' refers to, but Fred Anderson is also quoted as saying he'd like to get to $8 bil. in revenues, from $5.7 bil currently. For sure they'd need an increase across the entire line to get another $2.3 in revenues, but keep in mind that PowerMacs are big-ticket items. And there is a lot of pent-up demand for PowerMacs right now.
People who buy PowerMacs are also the people who buy the expensive displays, various hardware upgrades, and expensive pro software. So for each PowerMac they sell, they're probably making $3500-4000 in revenues. If they sold 500,000 more PowerMacs this year (which to me could very well happen if they bring out the 970 in the 1.8-2.0 range), they would get pretty close to the $2.3 bil in added revenues they're looking for. The XServes will also get a huge boost in sales if they came with the 970s.
If I knew that the 970 was a sure sure thing, I'd be investing a lot of money in Apple stock right now...
here here.
Moto has ruined apple's market share with their slow chips.
I could definitely see low powered 970s in laptops.
Re: Re: Re: 32 bit on 64 bit 970 issue
Thanks, now I got it.
Wouldn't it be possible for a 64 bit chip to handle 2 32 bit wide chunk of code in 2 simultaneous 32-bit calculations per clock cycle ? Then it would be actually better to program in 32 bit, and as most applications are already in 32 bit it should be a nice speed boost.
Just wondering
Thanks, now I got it.
Wouldn't it be possible for a 64 bit chip to handle 2 32 bit wide chunk of code in 2 simultaneous 32-bit calculations per clock cycle ? Then it would be actually better to program in 32 bit, and as most applications are already in 32 bit it should be a nice speed boost.
Just wondering
Re: Re: Re: Re: 32 bit on 64 bit 970 issue
It seems that this would be impossible by the same logic that the 128 bit doesn't allow 4 32 bit instructions inside a 128 bit instruction. i think this has to do with the nature of an instruction, but i never was too good with this stuff.
It seems that this would be impossible by the same logic that the 128 bit doesn't allow 4 32 bit instructions inside a 128 bit instruction. i think this has to do with the nature of an instruction, but i never was too good with this stuff.
Re: Re: Re: Re: 32 bit on 64 bit 970 issue
No, that is not the nature of the beast. If you want to be able to apply the same operation to multiple peices of data (i.e. add 2 32-bit numbers) then that is what a SIMD unit is for, SIMD stands for Single Instruction Multiple Data. The standard integer unit on a CPU only knows how to execute a single operation on the entire register, which on the PPC970 is 64-bits wide. Thus you can add two 64-bit (or smaller) numbers natively, but you cannot add two 32-bit numbers at the same time.
Now that I've said that, this doesn't prevent programmers from doing these tricks. If you know that 2 or more numbers won't overflow when added, then you can pack them into the register and add them, but it's a lot more housekeeping that the Altivec unit will take care of for you.
No, that is not the nature of the beast. If you want to be able to apply the same operation to multiple peices of data (i.e. add 2 32-bit numbers) then that is what a SIMD unit is for, SIMD stands for Single Instruction Multiple Data. The standard integer unit on a CPU only knows how to execute a single operation on the entire register, which on the PPC970 is 64-bits wide. Thus you can add two 64-bit (or smaller) numbers natively, but you cannot add two 32-bit numbers at the same time.
Now that I've said that, this doesn't prevent programmers from doing these tricks. If you know that 2 or more numbers won't overflow when added, then you can pack them into the register and add them, but it's a lot more housekeeping that the Altivec unit will take care of for you.
I think Altivec is a Motorola trademark, which should not be used with IBM processors.
I think that Velocity Engine is an Apple 'trademark' that Apple could allow both IBM and Motorola to use to refer to the SIMD-iness of the their processors. (Damn lawyers! )
I think that Velocity Engine is an Apple 'trademark' that Apple could allow both IBM and Motorola to use to refer to the SIMD-iness of the their processors. (Damn lawyers!
)Link
Here's an excellent overview of the PowerPC 970. My apologies if it's already been posted.
http://www-3.ibm.com/chips/products/powerpc/newsletter/dec2002/newproductfocus2.html
Here's an excellent overview of the PowerPC 970. My apologies if it's already been posted.
http://www-3.ibm.com/chips/products/powerpc/newsletter/dec2002/newproductfocus2.html