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Rumored pro chip
- Thread starter cmaier
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Apple Knowledge Navigator
macrumors 601
If they (Apple) go down the chiplet route, then the rumour of a 'G4 Cube' Mac Pro does make a lot of sense for those who don't need PCiE expansion. In its simplest form, they could offer 2-4 of the high-end M-series chip distributed evenly across the logic board, and fill 80% of the chassis with a heatsink.
It makes me wonder if the current Mac Pro will even get an AS upgrade, or if they'll stick with Intel for the rest of its lifecycle.
It makes me wonder if the current Mac Pro will even get an AS upgrade, or if they'll stick with Intel for the rest of its lifecycle.
They tried this, it was the Mac Pro 6,1. It was much derided for not having pci expansion.
Maybe the smaller Mac Pro will have some pci slots, but it would be a step backwards to include none.
Apple Knowledge Navigator
macrumors 601
That’s true. But if the source suggested that this new device be roughly half the size, where would that space be cut? There must be compromises somewhere.
CWallace
macrumors G5
Apple could comfortably at least halve the size of Mac Pro 7,1 by moving from Intel Xeon to Apple Silicon, reducing the maximum amount of RAM from 1.5TB, removing the internal space used by third-party storage enclosures for 3.5" SATA drives and reducing the number of PCIe slots from 8 to 4 or even 2. The space taken up by the cooling and power supply will be much smaller, as well, with these changes.
Sydde
macrumors 68030
Given that Intel themselves seem to be edging away from HT, it is difficult to envision circumstances that could lead Apple toward it. HT helped because x86 CPUs have long, narrow pipes that are sensitive to bubbles, so feeding two code streams into one pipe significantly reduces branch-miss and memory-stall type bubbles. Optimizing efficiency between two simultaneous threads, however, is a challenge that may cost more than one gains in performance.
The ARM coding scheme is much easier to fit onto a wide pipeline that can recover more quickly from stalling conditions due to its more parallel nature, the larger register file helps reduce memory stall issues, the branch predictor, AAUI, is scary-good and OoOE helps keep the pipe well fed.
In other words, the issues that Intel was tackling with HT simply do not exist on ARM, and are highly unlikely to at some point later. It is not a strategy that would benefit AS any time soon, if ever.
Actually the coding scheme is RISC not ARM. All ARM is is an ISA. And Apple Silicon is its own thing with a unique microarchitecture that leverages RISC for an extremely wide (8 wide) pipeline and extremely high parallelism.
That's the first I've heard anyone say that, and all the CPU's for PCs you can buy now are HT.
And yes, I know what HT does and how, but there'll just be another bottleneck that the M series processors will hit, that's all I'm saying...
No it doesn’t. It helps *x86* CPUs with multicore performance, because in x86 CPUs it’s difficult to keep the pipelines full (because of narrow issue, small register files, and difficulty with instruction reordering caused by too small a look-ahead window due to the difficulty of decoding). We have already seen that M1 does a remarkable job of keeping the pipelines full. So if the cores are already completely busy in M1, which they essentially are (when running a big multi-core job), how can HT add anything further? The processor would need to stop a running thread to substitute in another, even though the first thread hasn’t hit a bubble.
HT is a solution to problems caused by difficulties caused by CISC, and is of little benefit to CPUs that have heterogeneous cores that already run at very high IPC.
...and most programs are single-theaded, which means you can only send out one person at a time, so the bus won't work.
True, for most applications. However, if the task is massive and parallelizable the bus is more like trains. Or several trains. Or a super-tanker.
In video editing, machine learning, genetic algorithms and lots of scientific applications the motorcycle won‘t work
Apple Knowledge Navigator
macrumors 601
Good points. Perhaps they'll keep the 7,1 around for a while longer, for those that do want all those features. Apple was really pushing them after all.
diamond.g
macrumors G5
Not really weird, they just combine their “desktop” cores (which have HT) with their atom cores (which lack HT), so the total number of hardware threads is not a integer multiple ( is this even English?) of the core count.
diamond.g
macrumors G5
Ah that makes more sense... I hope all the best for Intel cause the (rumored) PL2 TDP is pretty crazy.
The leaks I’ve seen so far specified power limits similar to the current CPUs, did yiu find some differing informatio?
diamond.g
macrumors G5
Intel Alder Lake-S ES Desktop CPU With 16 Cores & 24 Threads Spotted, Up To 3.05 GHz Clocks & On Par With i9-11900K
A new Intel Alder Lake-S Core i9 Desktop CPU entry featuring 16 cores and 24 threads has been spotted over at UserBenchmark.
wccftech.com
That's what I said and meant.
I didn't mean specifically HT, just that they will hit a bottleneck and they'll have to do something the purists say would be bad. I'm of the other opinion, as long as it works and as long as it does increase performance -- it's a good thing. (and sometimes a great thing!) I'm mainly a software guy, I don't really care about the underlying hardware.
The M1 yes, but what about the follow-on CPU's? The M1 really isn't that fast, so as they ramp up, will it still keep the pipelines full, or is something going to slow down the instructions, I don't know the answer to that, and until I actually see it myself, I'm skeptical.
Off topic but I love reading through the comments on wccftech, it’s a giant cesspool.PL1 is 125W which isn't totally out of the ordinary for an Intel CPU, but the PL2.....Intel Alder Lake-S ES Desktop CPU With 16 Cores & 24 Threads Spotted, Up To 3.05 GHz Clocks & On Par With i9-11900K
A new Intel Alder Lake-S Core i9 Desktop CPU entry featuring 16 cores and 24 threads has been spotted over at UserBenchmark.
I think Alder lake is doing something similar to the M1, where it has big and little cores. (performance and power saving) But it's still supposed to have normal HT on all its cores from what I've read.
That was the thing I liked about the M1 the most, those little cores for background system stuff is something that makes a heck of a lot of sense to me. We'll see when it's actually released.
IMHO, to write good software, you need to understand your hardware to take full advantage of it.
I said I didn't care, not that I didn't know anything about it. 🙂 (I do have a degree in computer science and am a total OS geek..)
Not sure I agree with your statement though, at least now. Before, when we didn't have some of the tools we have now, yes it was extremely important, now, not so much.
I suppose it depends on what software is being written. I like to tinker with device driver codes, so my perspectives would be skewed in that direction.
I agree, that would be necessary to know the underlying hardware! Just about any OS work would need it. But I'm just a dull business IT Manager/Developer, I gave up doing Assembly and low level C decades ago. Where you have to know HW, I have to know systems.