The 3Ghz wall?

[nanofrog]

This might be dumb but…

Aren't we still limited by the mechanical hardware inside of our computers? HDD's for example seem to be a real bottleneck.

Maybe I'm just not understanding this but wouldn't we need to let the rest of the components catch up before we increase the processor speeds? Otherwise we might not see any real world gains.

A very good point.

But the bottlenecks have been addressed (i.e. there are solutions), they're just expensive. The IMC in the Nehalem architecture was a massive improvement for RAM, and HDD throughputs can be handled with RAID (but it's expensive).

In the case of optical, the memory and storage aspect are being developed simultaneously (fully optical system - CPU, RAM and mass storage). But it still needs time, as the development has been metered out over time, not a sudden massive effort.

But there's other tech that will be released prior to fully optical systems, such as LightPeak (and it will have a few generations, as it's supposed to be capable of 100Gb/s, but will initially release at 10Gb/s).

 

[psingh01]

Higher clock rates are available (in the 4ghz range) but these aren't marketed for consumer use. The POWER7 is one such chip. The G5 was a cheapo version of the POWER5, so if Apple had stuck with PPC there might be a "G7" chip based on this now.

As for the "3Ghz wall", cpu's have gotten more efficient over the years. Not only be adding more cores but by being able to do much more per clock cycle than before. A 3Ghz P4 gets less work done per clock than a 3Ghz C2D (even if you only count 1 core).

 

[Quad 2.5 G5 =)]

Higher clock rates are available (in the 4ghz range) but these aren't marketed for consumer use. The POWER7 is one such chip. The G5 was a cheapo version of the POWER5, so if Apple had stuck with PPC there might be a "G7" chip based on this now.

As for the "3Ghz wall", cpu's have gotten more efficient over the years. Not only be adding more cores but by being able to do much more per clock cycle than before. A 3Ghz P4 gets less work done per clock than a 3Ghz C2D (even if you only count 1 core).

I think the "GHz wall", for the Core2 line tops out around 3.3/3.0 for the Dual and Quad core processors, respectively. The E8500 runs at 3.16, and the E8600 (overclocker's dream) runs at 3.33. Also, the i5-670 runs at a stock 3.46, and the 660/661 run at 3.33 also. I think the limit for the processors isn't 3GHz, but 4GHz. But, it is good to be adding cores and QPI links, as opposed to FSB. The faster Intel ramps up a C2D, it won't mean much if the FSB is only 1333MHz. That would be like adding 2 lanes each way to a highway that only has on/off ramps that total 2 lanes each way. There's still going to be a bottleneck there. But now with the DMI in the Lynnfield that runs at 2.5GT/s, the system has more bandwidth, but that is taken up a bit more by the memory channels and PCI-E channels. The QPI in the LGA1366 (Core i7/Xeon), is the least likely to clog up, and, if I am not correct, the processors will have to climb to 8 or 10 cores at a higher speed to clog it up so that the bus between the processor and the other components is once again, the bottleneck of performance.

 

[mason.kramer]

Exactly. The Pentium 4's pipeline was known for having "do-nothing" stages added that simply allowed for electron propagation.

Yeah...I'm not forgetting about 'the laws of physics' when I say that we aren't up against theoretical limits.

You are talking about electron mobility, which is a function of the material and the field strength.

The problem you are probably alluding to is that mobility decreases as voltage decreases, but dropping voltage is the way to lower power dissipation. There are ways around the mobility barrier, however. One of them is use fewer layers in your silicon process, so that the electrons have less distance to travel (decreasing propagation time). The limit for this distance is set by electron tunneling (we don't want those electroncs randomly tunnel through the gate). However we aren't at the tunneling distance with current processes, meaning we can have fewer layers in future processes without hitting the limit. Anyway, as OCers can get to 4ghz with no voltage increase, mobility is not a barrier in current gen chips at least till there.

Also promising is the use of new semiconductors with higher electron mobilities, particularly the ones with pi cloud valence electrons such as graphene, which has a mobility 100x higher than silicon. Chips made out of graphene could be at 40ghz and dissipate 1/10th of the heat of the current gen. So, no, we have not hit theoretical limits.