Oh totally. I know that Apple doesn't have to copy Intel. I was just curious as to how M1's implementation differed from Ice Lake's (at least on the 2020 Intel 4-port 13" MacBook Pro; I have no clue if it's the same on the 2020 Intel Air or not)
They probably have a substantive overall design goal overlap because of this:
"...The other upside to the tightly coupled integration is that Intel stated that this method of TB3 is a lot more power efficient that current external chip implementations. However they wouldn’t comment on the exact power draw of the TB3 block on the chip as it corresponds to the full TDP of the design, especially in relation to localized thermal density (Intel was initially very confused by my question on this, ultimately saying that the power per bit was lower compared to the external chip, so overall system power was lower – they seemed more interested in discussing system power over chip power). Intel did state that the difference between an idle and a fully used link was 300 mW, which suggests that if all four links are in play, we’re looking at 1.2 W. ..."
www.anandtech.com
Integrating allows Apple to lower the power budget. They don't have to exactly copy Intel's implementation, but if there is a power consumption win out of it they are probably all over it.
The host targeted TBv3 controller is 2.4W .
Intel® JHL7540 Thunderbolt™ 3 Controller quick reference guide including specifications, features, pricing, compatibility, design documentation, ordering codes, spec codes and more.
ark.intel.com
The TBv4 retimer 0.75W
Intel® JHL8040R Thunderbolt™ 4 Retimer quick reference guide including specifications, features, pricing, compatibility, design documentation, ordering codes, spec codes and more.
ark.intel.com
So four ports with the legacy TBv3 style with discrete controllers : ~ 5W
Four ports with the new integrated+retimer style : ~ 2.7W ( 1.2 + 1.5 )
So in the rough ballpark of being a 50% power reduction. If you put that 'carrot' out in front of Apple they are probably going to go chase it. ( even more so if can trim some optional USB4 stuff and eek out some more savings.). It wasn't a question of whether Apple was eventually going to do down this route, but more a question of how soon.
These internal TB controllers are somewhat of a balloon squeeze though. For example :
Ice Lake (ICL) Client Configuration is Intel's successor to Cannon Lake, a 10 nm microarchitecture for mainstream mobile devices.
en.wikichip.org
When load up 3-4 6K displays and 2-3 PCI-e x4 v3 and core-to-PCH demands upon the backbone fabric is the overall throughput going to be there? Apple's fabric only has one DPv1.4 stream on it. Probably in part due to limitations of the GPU subsystem. But with better GPU display output systems attached to a unified backbone fabric just how much headroom is there going to be?
The real gap between Apple's and Intel's embedded implementations probably won't be exposed until Apple delivers some 4 port provisioned systems. If they add just one more DPv1.4 stream and Intel is sitting on four streams then that will be a gap. Apple will probably point to two XDR's is as many as most folks need so it is a more than reasonable trade-off.
Since Apple is the only system vendor customer that Intel has who regularly implemented systems with > 2 Thunderbolt ports , there is a pretty high probability that Apple was at least partially behind Intel implementing a basic 4 port TB implementation with their embedded solution. Most of their customers wre only going with 2, so Intel doing 4 was aimed at the general status quo. ( more so trying to get folks to move up in ports provisioned. )
So was Apple asking Intel to do four ports while at the same time doing the same internally. Probably. Would that lead to very similar looking implementations from the outside looking in? Yes. If they handed Intel the same general specification objectives as a "wish list" as they were using themselves... why would the implementations differ by a large amount from the external viewpoint?
I don't think going to settle question of whose implementation is "copying" or "proceeded" the other. When AMD weaves in ASMedia TB implementation library ( or does their own) when veiwed from outside the SoC package theirs too will probably have a high degree of similarities. (Especially if will try to go for Thunderbolt v4 certification eventually. )
Pragmatically TBv3 weaved in a XHCI USB "superspeed" controller into the TB controller package. If look at the M1 Mac's system report for USB there is an Apple-XCHI controller listed. Perhaps someone else's library design serving as the baseline design but Apple has put there "stamp" on the controller. ( how much they did "from scratch" or not is probably isn't all that material in the end. )
as I know that even the implementation of it on the 2020 4-port 13" MacBook Pro differs from that of pretty much every other Thunderbolt-equipped Intel based Mac that has ever existed before or since.
Yeah. A bit of a head scratchier why OWC's comparison didn't use that. Although in some sense, not surprising if trying to promote what a "huge difference" the M1 is (and make Apple more happy). The legacy implementation style is more indicative of most of the Macs out there.
I
