Triple channel, why four slots?

[xgman]

How credible is this information because I just cancelled my order 4x4gb and replaced it with 3x4gb

Apple really should ****ing provide some documentation.

exactly . . but this is from a person who actually tested the memory for Apple at Micron. This is the best source I have been able to come up with. Regardless of the 8gb testing, it is confirmed that Westmere is dual channel memory. Again thsi is only for the six core and 12 core 1333 systems!! I too called and had Transintl send my returned 4gb stick back.

here is a good explanation of the Westmere. Bit about the memory about half way down:

http://techgage.com/article/intel_reveals_westmere_32nm_roadmap/

 

[skiffx]

exactly . . but this is from a person who actually tested the memory for Apple at Micron. This is the best source I have been able to come up with. Regardless of the 8gb testing, it is confirmed that Westmere is dual channel memory. Again thsi is only for the six core and 12 core 1333 systems!! I too called and had Transintl send my returned 4gb stick back.

here is a good explanation of the Westmere. Bit about the memory about half way down:

http://techgage.com/article/intel_reveals_westmere_32nm_roadmap/

Im on the phone with Apple right now gonna see if I can get any of the engineers to confirm it, because Ill need to again call transintl and tell them to send my original 4x4gb bacl

Edit: Yeh once again Apple tech proves to be 'knowledgeable' said that the engineers said that it will run in dual and when needed switch to triple, which makes as much sense as ....

Anyway IM calling Transintl and getting 4x4

 

[xgman]

I doubt anyone you can get on the phone at Apple will have any idea other than the specs on the website.

 

[xgman]

Probably if any of us had googled Westmere, we would have quickly seen that it uses a dual channel memory controller. I've never been one for reading the instructions.

 

[skiffx]

I doubt anyone you can get on the phone at Apple will have any idea other than the specs on the website.

Yeh, anyway thank you for the last minute heads up

 

[xgman]

Westmere’s memory controller can drive two DIMMs per channel at the full 1.33GT/s. Current Nehalem systems (and most AMD systems) run two DIMMs per channel at reduced bandwidth; Nehalem’s memory controller operates two DIMMs per channel at 1.06GT/s, sacrificing about 20% of the bandwidth.

the Nehalem core supported three channels of DDR3 memory, but you could only acheive maximum speed (1333mhz) with a single DDR3 DIMM per channel. With Westmere, Intel has tweaked the memory controller for performance, so now you can still get to that 1333mhz number with two DIMMs installed per channel. An end user can now buy cheaper, lower density DIMMs without fear of performance degradation. The new and improved memory controller also supports new low-voltage DDR3 memory modules.

 

[skiffx]

Awesome, so now more, faster ram

 

[xgman]

Now I'm not so sure. Conflicting info until we have part numbers for the processor and the motherboard. It could be either way.

 

[xgman]

best I can figure is the W3680 is a workstation processor, not a server processor and would go into a Intel WX58EP motherboard. Now, I can't confirm that is the board the Apple is based on, but no server board is listed as compatible with the W3680. That means our original thoughts on the 3 channels are correct. I am going to test 8gb x 3 as soon as I can. Sorry for any confusion. Apple could have given us a memory config lesson on this but .. . .

 

[deconstruct60]

here is a good explanation of the Westmere. Bit about the memory about half way down:

http://techgage.com/article/intel_reveals_westmere_32nm_roadmap/

If you are refering to:
"Unlike Core i7, however, mainstream desktop/mobile Westmere chips will not feature a QPI bus or a triple-channel memory controller. Rather, we'll revert to a dual-channel controller and have no QPI clock to worry about (what new factors will come into overclocking is yet to be seen).
"
The key factor there is that referring to the desktop versions. Not the Xeon or "i7 Extreme" implementations of the architecture. The desktop and high end mobile versions strip off functionality to do market segmentation. One of those is throttling memory bandwidth. So the i7's in the iMac do have fewer memory channels. On very high load factor workloads they do a worse job.

At one point everything "i7" was in the "Extreme" classification. Now "i7" labelled parts can have 2 or 3 channels depending upon on how "high end" they are. By itself says nothing about dual or triple anything.


However, that is nothing to do with the Mac Pros' Xeon in either the 2009 or 2010 generations.

 

[xgman]

My original assumptions were incorrect. What I did not understand in that the W3680 is a "workstation" processor and NOT a server board processor according to Intel's compatibility sheets. Therefore the most likely board Apple is using is based on the Intel WX58BP.

http://www.intel.com/products/workstation/motherboards/wx58bp/wx58bp-overview.htm

 

[barefeats]

Someone referenced a graph I posted where I used the DLT stress test showing the 8-core Nehalem with 6 memory modules with much higher bandwidth than with 8 memory modules. I've learned since then that if you run the bandwidth test so that you only use the first 12G of the 16G config, the bandwidth is the same for both memory configs.

Also I stated that most apps can't saturate the memory bandwidth so it should not make a difference in the real world. I can back that up with test data showing the Nehalem with 16GB of RAM equaling or beating the time it took the 12GB config to complete After Effects CS5 renders, Compressor 3.5 renders, Cinebench 11.5 CPU test, and Geekbench 64 bit test.

In the AE CS5 render, 14G of the 16GB of memory was in use -- which brings me to my third point. It's often better to have sufficient memory than to have the perfect theoretical memory config.

 

[VirtualRain]

Someone referenced a graph I posted where I used the DLT stress test showing the 9-core Nehalem with 6 memory modules with much higher bandwidth than with 8 memory modules. I've learned since then that if you run the bandwidth test so that you only use the first 12G of the 16G config, the bandwidth is the same for both memory configs.

That's consistent with what I read on Anandtech about Intels first Nehalem/X58 skull trail desktop motherboard that also came with four DIMM sockets across a tri-channel config. (incidentally The Mac Pro logic boards are apparently designed by Intel). Like the Mac Pro, this Skulltrail board had people scratching their head about how 4 DIMMs would be handled on a tri-channel controller.

Anand said that with all 4 DIMMS populated (say 4x2GB), the memory controller would interleave across all three channels up to 6GB but after that, the last 2GB (last DIMM socket) would obviously have nothing else to interleave with so that upper memory range would have the effective bandwidth of a single channel.

So, perhaps it's not defaulting to dual channel mode with 4 DIMMs?

Edit, here's the source... http://www.anandtech.com/show/2658/5

With a three-channel DDR3 memory controller, Nehalem requires the use of three DDR3 modules to achieve peak bandwidth - which also means that the memory manufacturers are going to be selling special 3-channel DDR3 kits made specifically for Nehalem. Motherboard makers will be doing one of two things to implement Nehalem's three-channel memory interface on boards; you'll either see boards with four DIMM slots or six.

In the four-slot configuration the first three slots correspond to the first three channels, the fourth slot is simply sharing one of the memory channels. The downside to this approach is that your memory bandwidth drops to single-channel performance as you start filling up your memory. For example, if you have 4 x 1GB sticks, the first 3GB of memory will be interleaved between the three memory channels and you'll get 25.6GB/s of bandwidth to data stored in the first 3GB. The final 1GB however won't be interleaved and you'll only get 8.5GB/s of bandwidth to it. Despite the unbalanced nature of memory bandwidth in this case, your aggregate bandwidth is still greater in this configuration than a dual-channel setup.

 

[trankdart]

So, perhaps it's not defaulting to dual channel mode with 4 DIMMs?

I think that Anandtech review is a bunch of malarky. Take a look at this Fujitsu white paper. I understand it's for high-powered servers and not Mac Pro's, but the basic issue of how asymmetric memory sticks are grouped for interleaving by the system at power-up time is the same. In particular, look on page 13 for this:

If the GB per channel are different, the physical memory is split in areas with different interleaving. The aim in this situation is to avoid areas with 1-way interleave. The BIOS thus resolves a
2- 1- 1
with identical 4 GB strips (which is sensible for reaching a total capacity of (16) GB, for example) into two 2- way halves as follows: **(TD note: the Fujitsu white paper only talks in terms of dual-processor boards, I've removed the redundant data for the second processor)

1 - 1 - 0 (50% of memory capacity) 2-way interleaving
1 - 0 - 1 (50%) 2-way interleaving

Instead of

1 - 1 - 1 (75%) 3-way interleaving
1 - 0 - 0 (25%) 1-way interleaving

The first arrangement is what Fujitsu does and what a sane person would do with four sticks on 3 channels (allocate the DIMMs into two pairs using all 3 channels for maximum interleave). The second arrangement is what Anandtech says the Nehalem architecturee is limited to doing. This limit is obviously in the mind of the Anandtech reviewer, not in the Nehalem architecture.

I have to believe that Intel engineers designing boards for Intel CPU's would do the sane thing, not the Anandtech thing.

TD