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TSMC has achieved better-than-expected results in trial production of its 2-nanometer chip technology, with yield rates exceeding 60%, according to Taiwanese supply chain sources (via Liberty Times Net). The news suggests the company is well-positioned to begin 2nm mass production in 2025, which could see its use in Apple's iPhone 18 Pro models the following year.

tsmc_semiconductor_chip_inspection_678x452.jpg

The semiconductor manufacturer is reportedly conducting risk trial production at its Baoshan facility in Hsinchu, northern Taiwan, where it has implemented a new nanosheet architecture that promises a significant advancement over the current 3nm FinFET process. The company plans to transfer this production experience to its Kaohsiung plant for mass manufacturing, according to the report.

TSMC's progress bodes well for Apple, with a September report from analyst Ming-Chi Kuo and a more recent rumor claiming that Apple's 2026 iPhone 18 Pro models will exclusively feature chips built on TSMC's 2nm process and 12GB of RAM. The standard iPhone 18 models are expected to continue using an enhanced 3nm process due to cost considerations.

The 2nm process is said to be generating substantial interest from potential customers, particularly in the AI sector. Indeed, company CEO C.C. Wei has noted unexpectedly high demand for the upcoming 2nm technology, suggesting production at scale will be ramped up as soon as is possible to meet that demand.

TSMC's roadmap includes the 2026 introduction of an A16 process (1.6nm-class – not to be confused with Apple's chip nomenclature), which will combine Super Power Rail (SPR) architecture with nanosheet transistors. SPR is expected to provide an 8% to 10% performance increase at the same voltage and complexity, a 15% to 20% power demand decrease at the same frequency and transistor count, and a 7% to 10% chip density increase, depending on the design.

Article Link: TSMC 2nm Chip Production Hits 60% Yield, on Track for iPhone 18 Pro
 
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Apple has to be making a fortune by developing their own SoCs vs buying from Intel. Wish the world would put a strategy in place to ensure safety of all places where TSMC operates. And then there’s the problem of them supposedly not following laws in selling AI chips??? What would happen if TSMC is no more due to other issues? I am not normally one to defend an Apple or its supplier, but in this case I do. TSMC is a magical company and believe worth 9th largest market cap of any publicly-traded company.
 
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iPhone 18 is similar to the iPad PRO 2024 and the Apple Watch 10 a must have device in case you're using an older version.

These are quantum leaps in usability and performance that are worth considering.

Not everyone is updating or on a yearly replacement cycle. In my case the iPhone 14 is doing very well still and the iPad PRO from 2018 is till being used as was my iPhone 4 until September.

2nm will make a huge impact on battery life, speed, NE and thus machine learning and I hope we're seeing an iPhone with 2 TB for the first time ever.

Looking forward to it.
 
good. I'll wait for the M6 Max Mac Studio. Built on 2nm.

I personally think Technology is going to crawl after 2nm chips.
 
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meanwhile intel is rumored to be at 10% yield on 18A

There are two major inputs to yield. Defect density and size of the die. Larger dies have lower yield rates for the same defect density.

Intel has reported that they have about 0.4 defect density ( before HVM status. )

" ... Generally, it is considered that a defect density below 0.5 defects per square centimeter is a good result, so even keeping in mind that defect density varies by process and application, Intel 18A’s defect density of 0.4 defects per square centimeter is a reasonably good result considering its timing. Yet, TSMC’s N7 and N5 technologies had a defect density of 0.33 at a similar development stage, and when TSMC’s N5 reached mass production, its defect density dropped to 0.1. Yet, TSMC’s N3 started with a higher defect density but matched N5’s defect rate after five to six quarters ..."



For the nominal die settings for the above calculator, 0.4 gives a yield rate of 77% . No where near 10%.

However if try to make reticle busting sized dies that are popular with Nvidia and Broadcom that has problems. For example 25 mm x 30 mm dies drop all the way to ... wait for it .... 10% . Coincidence or source of the disconnect?

[ NOTE: if move that 25 mm x 30 mm die to 0.3 defect rate it jump to 15%. ]


The implementation design is also another factor. ( e.g., Nvidia had to tweak Blackwell to get around some packing yield issues. ) Don't need 'perfect' dies to have a binned working product if have some redundancies . It is more straightforward cheaper to have a lower defect density.


Is TSMC talking reticle sized test dies for their 60% ? Nope. Pretty decent chance what we have here is 'apples to oranges' stuff. Semiaccurate and Korean ( possible Samsung Foundry fans ) throwing 'doom and gloom' at Intel. Intel is off from TSMC's defect density, but 10% is suggestive that probably not talking standard test dies.

18A would not be a good match for Apple because Apple isn't big on chiplets. The 'Max' variant is a relatively big die ( not in the reticle busting zone, but 'big'. ). The huge potential problem for Intel is that their data center dies have tended to run somewhat large ( AMD is making more true chiplets to compose their solutions). 0.4 would make it hard to be profitable unless they start using substantively smaller dies as basic building blocks.

It also cuts Intel out as being a "mega AI die" boundary options. The boundary isn't going to be able to ride the AI hype train. Broadcom probably is twitchy if not doing chiplets ( glue two 600+ mm^2 dies together isn't really 'good' chiplet design. It is really just a means of making something 'even bigger' rather than functional decomposition. ). It is going to be hard for Intel to quickly get some "cost doesn't matter" AI clients in the intermediate term. Nor will their discrete GPU comes back in quicker ( if it survives).

The short term problem for the Intel foundary is that the still only have 'one' big customer. The client PC SoC shop that wants keep the single threaded drag racing crown and the expensive multicore crown. 18A might work well enough for that. But it isn't what the upper 20% die sized folks are looking for. It is a better fit for perhaps folks ding RISC-V / Arm speciality SoCs that are not trying to bust into the datacenter AI/HPC market.

Intel has lots more work to do on better design kits and ecosystem, for broad ranging fab offerings , and establishing expectations with external customers. But 10% yield is likely is just 'doom and gloom' that sells clicks and ad (click bait).
 
A very long time ago, I remember hearing a report on public radio saying that the semiconductor industry had an insurmountable barrier to overcome: due to the laws of physics and the wavelength limitations of light energy when etching the silicon wafer through a stencil, there was a 13nm chip size limit. Something tells my memory is faulty, or I missed the technological changes which have happened.
 
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A very long time ago, I remember hearing a report on public radio saying that the semiconductor industry had an insurmountable barrier to overcome: due to the laws of physics and the wavelength limitations of light energy when etching the silicon wafer through a stencil, there was a 13nm chip size limit. Something tells my memory is faulty, or I missed the technological changes which have happened.
Yes, however a couple decades ago many of the chip manufacturers (not Intel initially, but they are doing it now too to sound competitive) starting using marketing terms to name their manufacturing processes and while chip density has continued to increase the density isn't as much as the name would suggest. For example the N3E which Apple currently uses in the A18 and M4 chips has a transistor gate pitch of 48 nm and an an interconnect pitch of 23 nm so they haven't actually reached the physical limits of what you can do with silicon yet.
 
A very long time ago, I remember hearing a report on public radio saying that the semiconductor industry had an insurmountable barrier to overcome: due to the laws of physics and the wavelength limitations of light energy when etching the silicon wafer through a stencil, there was a 13nm chip size limit. Something tells my memory is faulty, or I missed the technological changes which have happened.
It's not your memory that's faulty. It's the premise that we have reached the limit of memory technology. We may or may not be nearing the limit for silicon, but scientists and engineers are working on other means of storage. I've seen crystal, diamond, even water! being tested as potential improvements. And I bet there are a whole lot more coming. Anyone interested in a quantum iPhone?
 
Computers are already fast enough, being less thirsty so that an iPhone can last a week or 2 on a single charge is the next thing.
Batteries used to last 1to 2 weeks, they were fairly dumb phones though.
 
meanwhile intel is rumored to be at 10% yield on 18A
Intel will probably go under next year and sold. The’ve been making poor decisions since 2005 when they had a chance to buy Nvidia. Then when they had the chance to make mobile chips for the original iPhone.
 
Yearly improvements of the chips powering the iPhones have been impressive. No doubt the next one with 2nm chip will be a very powerful one.
 
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