The end of Slicon node reduction is near. Maybe 1.5 nm or so. What next?
That has been the refrain since at least the 1980s, and engineers (some who I went to grad school with) have found ways around it. Eventually, it will happen, but ramping up cores has been a way to increase performance, software to use them efficiently has been the bottlenec. (There was also the CISC vs RISC debate. )