TSMC to Begin Production of 3nm Chips This Year

[MacRumors]

Apple chipmaking partner TSMC is "on track" to begin risk production of a 3-nanometer fabrication process in 2021, followed by volume production in the second half of next year, according to the foundry (via DigiTimes).

"Our N3 technology development is on track with good progress," said TSMC CEO CC Wei at the company's earnings conference call on January 14. "We are seeing a much higher level of customer engagement for both HPC and smartphone application at N3 as compared with N5 and N7 at a similar stage."

TSMC has been gradually miniaturizing its process over the years, going from a 16nm A10 chip in iPhone 7 models to a 5nm A14 chip in iPhone 12 models.

Apple will use a 5nm+ A15 chip for the 2021 iPhones, and TrendForce believes it is highly likely that the A16 chip in 2022 iPhones will be manufactured based on TSMC's future 4nm process, suggesting the new 3nm technology will likely be used for a potential A17 chip and potentially other future ‌Apple silicon‌ Macs if the company follows previous years. The 3nm process yields 30 percent and 15 percent power consumption and performance improvements over the 5nm process.

In other related news, TSMC triggered a global chip stock rally on Thursday, after outlining plans to pour as much as $28 billion into capital spending this year – more than half its projected revenue for 2021, reports Bloomberg.

TSMC's capital spending for 2021 is expected to be $25-28 billion, compared with $17.2 billion the previous year. About 80% of the outlay is said to be be devoted to advanced processor technologies. The foundry saw revenue climb 23% to $5.1 billion in the December quarter – a new record, achieved largely thanks to the success of Apple's iPhone 12 series.

TSMC also intends to build and operate an advanced semiconductor factory in Arizona, with construction planned to start in 2021 and production targeted to begin in 2024. TSMC estimates that its total spending on this project, including capital expenditure, will be approximately $12 billion from 2021 to 2029, with the facility expected to create over 1,600 high-tech professional jobs directly.

Article Link: TSMC to Begin Production of 3nm Chips This Year

 

[Serban55]

Begin production...not mass production...so expect 3nm to be offered into products next year
This year will be testing and so on...but its great news that in 2022 we will have 3nm

 

[yurc]

Intel : we barely move to 7nm

 

[jameswilby]

to a 7nm A14 chip in iPhone 12 models

Aren't they 5nm?

 

[Freeangel1]

I really think 3mn will be the limit. I will be extremely surprised if they can go any smaller
just more cores is all that's left.

 

[farewelwilliams]

digitimes


yawwwwwwn

move along

 

[SBlue1]

3nm is insane. This is just 15 layers of silicone atoms!

 

[ruka.snow]

Intel : we barely move to 7nm

Measuring different things. 10nm Intel and 10nm TSMC are not comparable. One is measuring how many sofa's you can fit in a room, the other is measuring how many coffee tables you can fit in a room.

 

[kneezmo]

Aren't they 5nm?

Yep. They are wrong

 

[Mike_Trivisonno]

They're almost out of nanos.

 

[ZzapDK]

3nm? I thought we had reached the limit where "bleeding" was so prominent that it was impossible to reduce the size this small? What IS the lowest limit currently?

 

[MrDerby01]

Measuring different things. 10nm Intel and 10nm TSMC are not comparable. One is measuring how many sofa's you can fit in a room, the other is measuring how many coffee tables you can fit in a room.

Hi! Interesting reply.. Your original reply caught my attention. I agree with you there are different measuring techniques. I watched a documentary on Fractals and how measurements are cut in half over and over. You could measure land differently on a map depending on the size of the ruler. Each smaller ruler would provide a finer detail of accuracy in the distance of the land, shape ... ect.. My point is.. I find it interesting that we have standards for everything from ICANN, PCI standards and so forth but... To your point it seems we have no agreed on "Standard" means of measurement withing the PC world. Am I correct?

 

[0924487]

3nm? I thought we had reached the limit where "bleeding" was so prominent that it was impossible to reduce the size this small? What IS the lowest limit currently?

"There is a fundamental limit of exceptional Engineers because there just aren't that many" - Elon Musk.

 

[ruka.snow]

Hi! Interesting reply.. Your original reply caught my attention. I agree with you there are different measuring techniques. I watched a documentary on Fractals and how measurements are cut in half over and over. You could measure land differently on a map depending on the size of the ruler. Each smaller ruler would provide a finer detail of accuracy in the distance of the land, shape ... ect.. My point is.. I find it interesting that we have standards for everything from ICANN, PCI standards and so forth but... To your point it seems we have no agreed on "Standard" means of measurement withing the PC world. Am I correct?

There used to be a 'standard' but now each manufacturers process is different. It has been proposed to now measure density, in which case Intel could potentially 'win' as their 10nm process has more density than TSMC's 7nm process.

A Density Metric for Semiconductor Technology [Point of View]

Since its inception, the semiconductor industry has used a physical dimension (the minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. As a replacement, we propose a density metric, which aims to capture how advances...

ieeexplore.ieee.org

 

[wanha]

I really think 3mn will be the limit. I will be extremely surprised if they can go any smaller
just more cores is all that's left.

Yes, it's all that's left in this particular paradigm. But there will always be a new paradigm, and I will be curious to see what that will be.

 

[NotTooLate]

Measuring different things. 10nm Intel and 10nm TSMC are not comparable. One is measuring how many sofa's you can fit in a room, the other is measuring how many coffee tables you can fit in a room.

The process race is interesting , and your comment is correct in the sense that they basically make up that number now days , BUT TSMC are marching forward with their process R&D , and on their best nodes TSMC have better density , lower leakage , they have lower Vth for the same speed switching (i.e better performance for the same voltage).

So although we cant compare just this number vs the other , in today`s world TSMC are better then Intel on their cutting edge nodes and at the rate TSMC are executing i would assume it will remain this way in the foreseeable future.

Lastly , both Intel and TSMC are making incremental progress between major process breakthroughs , so Intel 14nm of today (14nm+++++) is much better then the 14nm that was first shipped , TSMC likes also uses that + variant but usually for 1 iteration , then they do an intermediate node (4nm in this case).

TLDR - putting all of that naming scheme aside , TSMC has a better process technology then Intel when matching the best nodes head to head.

 

[gridlocked]

Intel should have bought TSMC a long time ago, problem solved. Then they could stuff sofas, coffee tables, refrigerators and anything else they wanted into a room.

 

[hagjohn]

It is amazing to see the difference in tech between 1990's to now.

 

[djcerla]

I remember reading “under 40 nm is physically impossible” comments.

 

[stringParameter]

3nm is insane. This is just 15 layers of silicone atoms!

Jonny Ive: "it's still not thin enough"

 

[stringParameter]

Intel should have bought TSMC a long time ago, problem solved. Then they could stuff sofas, coffee tables, refrigerators and anything else they wanted into a room.

What?

 

[adamjackson]

Apple really knows how to pick their partners.

 

[pshufd]

Can we build semi-conductors from subatomic particles?

 

[ruka.snow]

The process race is interesting , and your comment is correct in the sense that they basically make up that number now days , BUT TSMC are marching forward with their process R&D , and on their best nodes TSMC have better density , lower leakage , they have lower Vth for the same speed switching (i.e better performance for the same voltage).

So although we cant compare just this number vs the other , in today`s world TSMC are better then Intel on their cutting edge nodes and at the rate TSMC are executing i would assume it will remain this way in the foreseeable future.

Lastly , both Intel and TSMC are making incremental progress between major process breakthroughs , so Intel 14nm of today (14nm+++++) is much better then the 14nm that was first shipped , TSMC likes also uses that + variant but usually for 1 iteration , then they do an intermediate node (4nm in this case).

TLDR - putting all of that naming scheme aside , TSMC has a better process technology then Intel when matching the best nodes head to head.

I should clarify, I don't believe Intel 10nm is ahead; it just isn't 1:1 comparable with 10nm from other companies. My point is more that people think they're years behind when in fact it is a vastly more complex matter with a lot of marketing blurring reality.

 

[cal6n]

3nm? I thought we had reached the limit where "bleeding" was so prominent that it was impossible to reduce the size this small? What IS the lowest limit currently?

Nearest neighbour spacing in a Silicon crystal lattice is 0.235nm, so the process can't go below double that purely on space constraints.

I don't know the physical limit for maintaining electrical separation between two surfaces. Even ambient thermal considerations will play a part at that scale. What is certain is that TSMC's process is within an order of magnitude of the limit.

I am officially awe-struck!