When Will Apple Silicon Support PCIe 5?

[sideshowuniqueuser]

THere are no conventional NVMe SSDs in a Mac. Apple's SSD is not a conveniental NVMe SSD. It may present to the user at the OS utilities as such, but it is not. There is no NVMe SSD slot in any of the plain Mn powered Mac systems at all. Not in the Mn Pro or Mn Max either.

The modules in a Mac Studio or Mac Pro are NOT SSDs.



For the Mac Pro are no native M.2 slots on that system either. To add a M.2 (or other standard format SSD; ES1 , U.2 , etc. ) you would need a card. If select a card with a PCI-e v5 to v4 switch on it is already enables that you could put two x4 PCI-e v5 SSDs in a Mac Pro and it would work ( in a x16 PCI-e v4 slot. x4 v5 == x8 v4. 2 * x8 = x16 . Done. )

You can't to 3-4 v5 SSDs , but 1-2 is already covered. It won't be the cheapest possible path, but the Mac Pro at $6K is already not the cheapest possible path.

right, so how does the "not ssd" talk to the rest of the system?

 

[sideshowuniqueuser]

Apple does not use off the shelf PCIe NVMe SSDs. The "rules" you've internalized from PCs do not apply.

Apple integrates their own SSD controller directly into the M-series SoC. It connects to the internal "Apple Fabric" bus that links CPUs and high bandwidth peripherals to DRAM.

This SSD controller connects to flash modules over standard x1 PCIe links, one per module. (No, it's not a proprietary offshoot of PCIe, @deconstruct60, please don't confuse things like you so often do. Lots of your post up there was just nonsense.)

An Apple flash module is several flash memory die packaged together with a PCIe-to-NAND bridge IC designed by Apple. These bridges are not full SSD controllers - they don't implement the flash translation layer which does all the LBA-to-physical mapping and wear leveling. They just make it possible to read and write flash memory over PCIe.

The number of x1 PCIe lanes available for flash modules depends on which SoC you have. For base M1/M2/M3, it's 4 lanes (so, 4 modules maximum). For M1/M2/M3 Pro/Max/Ultra, it's 8 lanes, or 8 modules maximum. This means Apple already has the potential for SSD throughput equivalent to Gen5 x4 M.2 SSDs - gen4 x8 is the same bandwidth.

Getting angry because Apple hasn't jumped on PCIe gen 5 yet is silly. There's not much market penetration of gen 5 yet, and the most important thing which might make use of it (GPUs) isn't a big deal on Apple Silicon since Apple has chosen to not support third party GPUs.

where do you get all this info from?

 

[Appletoni]

Just wondering if/when Apple Silicon will support PCIe 5? By extension, when will Thunderbolt support PCIe 5 as well?

What will a MacBook 2024 offer compared to the high-end maxed out laptops 2024?

It was 2013 when i upgraded from 4 to 8 GB. And 2021 when i got 16GB. So i guess it will be another 30+ years till i will be in need for that 3 digits amount of ram

forums.macrumors.com

 

[mr_roboto]

where do you get all this info from?

Mostly from following key people in the Asahi Linux porting project on social media. Hector Martin has posted a lot of info he's discovered about the SSD architecture while reverse engineering Apple Silicon Macs.

 

[Melbourne Park]

While GPU coupling is not going to happen, fast external storage should be a benefit with M processors for some Mac buyers. And those are the ones who buy the high end Macs. A new gen Ultra without T5 will make then hesitate because another revision will have to have T5. And Thunderbolt "share" seems very attractive for small work groups. Or perhaps, the iPhone guys are really calling the shots and Apple will never gain T5. And Thunderbolt is Intel ... I'm not sure how well Apple and Intel get on these days.

 

[Marx55]

What PCIe version have the new Macs with M4 chips and Thunderbolt 5?

Which values show at "Apple - About This Mac - More Info - System Report - MVMExpress" for
Link Width and for Link Speed?

Reference:
PCI Express

PCI Express - Wikipedia

en.wikipedia.org

 

[mr_roboto]

What PCIe version have the new Macs with M4 chips and Thunderbolt 5?

Which values show at "Apple - About This Mac - More Info - System Report - MVMExpress" for
Link Width and for Link Speed?

The NVMe controller for Apple Silicon Mac boot SSDs is part of the main SoC, not a separate chip. If you bring up that page in System Information.app, it does not report PCIe link width and speed because there's literally no PCIe link.

 

[penguinlust]

Allegedly the M5 chips have PCIe 5 support, so there's your answer.

 

[pshufd]

I have a new Lenovo and it's PCIe 4 but the SSD speeds are 6K+ MBps. Are the base M4s PCIe 3?

We also build a desktop this year with an MSI Tomahawk X870E which supports PCIe 5 and has two NVMe Gen 5 slots and two Gen 4 slots. I think that you could get motherboards with PCIe Gen 5 in 2024 but I don't know how far back support goes. There are Windows with PCIe Gen 5 like the MSI Titan 18.

This thread is back from 2021 and Apple's SSD speeds, particularly on the base models, was pretty slow compared modern speeds.

 

[Pressure]

Apple Silicon doesn't use PCIe for internal storage.

Perhaps they moved to faster NAND or more NAND modules for the base model.

 

[leman]

I have a new Lenovo and it's PCIe 4 but the SSD speeds are 6K+ MBps. Are the base M4s PCIe 3?

If I remember correctly, M2 already supported PCIe gen 4, so M5 might even have gen 5. No way of knowing without doing some low-level digging. But the SSD is not driven via the PCIe bus, that’s only for thunderbolt.

Apple Silicon doesn't use PCIe for internal storage.

Perhaps they moved to faster NAND or more NAND modules for the base model.

They don’t use PCIe lanes for the SSD, the protocol is still PCIe based (I think it was two or four lanes?). It is entirely possible that the higher speeds are enabled by upgrading the baseline PCIe tech.

 

[Pressure]

They don’t use PCIe lanes for the SSD, the protocol is still PCIe based (I think it was two or four lanes?). It is entirely possible that the higher speeds are enabled by upgrading the baseline PCIe tech.

They still need faster NAND modules to saturate the available bandwidth 😅

They used two 1600MT/s NAND modules for the base models (up to 3.2 GB/s) until the M5. The fact that the new M5 can do 4TB certainly points to more NAND modules being used (more lanes, higher speed).

 

[Basic75]

They don’t use PCIe lanes for the SSD, the protocol is still PCIe based (I think it was two or four lanes?)

You're saying they are using PCIe between the SSD controller and the rest of the SoC? Perhaps they're using the protocol with a custom PHY?

 

[leman]

You're saying they are using PCIe between the SSD controller and the rest of the SoC? Perhaps they're using the protocol with a custom PHY?

Probably the second option, yes. From what I understand, they do not hook the SSD to the standard PCI-e lanes provided by the PCI-e controller. Rather, the SSD controller is a separate IP block and it has its own dedicated connection to the SSD. But this connection was still supposed to be based on PCI-e a few years ago. Maybe they went fully custom in the meantime, no idea. Or maybe I am just confused

 

[Krevnik]

Probably the second option, yes. From what I understand, they do not hook the SSD to the standard PCI-e lanes provided by the PCI-e controller. Rather, the SSD controller is a separate IP block and it has its own dedicated connection to the SSD. But this connection was still supposed to be based on PCI-e a few years ago. Maybe they went fully custom in the meantime, no idea. Or maybe I am just confused

Last time I had a debate on this elsewhere, the SSD controller does appear like an NVMe device, with the same hardware registers/etc. So an NVMe driver can quite simply just talk to it like any other NVMe drive, once it knows where the registers are. Asahi Linux had to supply kernel patches to do just that, and bypass the assumption that NVMe = PCIe.

As you point out, it's not hooked up to a PCIe link, and instead directly to the internal bus Apple uses.

If I remember correctly, M2 already supported PCIe gen 4, so M5 might even have gen 5. No way of knowing without doing some low-level digging. But the SSD is not driven via the PCIe bus, that’s only for thunderbolt.

And a couple peripherals, IIRC. I think the Mini and Studio put Ethernet out on the end of a PCIe lane or two. The 2024 Mini has a Broadcom PCIe Gigabit ethernet controller on the logic board. The M3 MBP I have says the SDXC controller is sitting at the end of a PCIe link, and iFixit seems to point to a Genesys part on the logic board that is a PCIe SD Card reader controller.

So there are a couple extra lanes available for these sort of peripherals that go beyond what's dedicated for Thunderbolt.

 

[mr_roboto]

Last time I had a debate on this elsewhere, the SSD controller does appear like an NVMe device, with the same hardware registers/etc. So an NVMe driver can quite simply just talk to it like any other NVMe drive, once it knows where the registers are. Asahi Linux had to supply kernel patches to do just that, and bypass the assumption that NVMe = PCIe.

There was more work than that. Apple's NVMe controller has nonstandard NVMe protocol extensions to support their Secure Enclave based full disk encryption. They also put it behind an Apple IOMMU, and the entire complex has one of their ASC coprocessors to manage it.

As you point out, it's not hooked up to a PCIe link, and instead directly to the internal bus Apple uses.

And a couple peripherals, IIRC. I think the Mini and Studio put Ethernet out on the end of a PCIe lane or two. The 2024 Mini has a Broadcom PCIe Gigabit ethernet controller on the logic board. The M3 MBP I have says the SDXC controller is sitting at the end of a PCIe link, and iFixit seems to point to a Genesys part on the logic board that is a PCIe SD Card reader controller.

So there are a couple extra lanes available for these sort of peripherals that go beyond what's dedicated for Thunderbolt.

The Apple NVMe SSD controller does make use of PCIe, but it's on the side facing the flash. The side facing the rest of the SoC connects through "Apple Fabric", Apple's on-die interconnect.

Conventional NVMe controller ASICs talk to NAND flash die through a bunch of ONFI / Toggle NAND channels. Much like DDRn channels, an ONFI/Toggle channel is a parallel interface consisting of data (8 or 16 bits) and control/clock signals.

A single ONFI/Toggle channel has relatively low performance, so you need a lot of channels to build a large, fast SSD. Even though the channels are relatively narrow, the quantity you need adds up to a lot of pins. That's okay in a standalone ASIC whose only job is to be a SSD controller, but I think it was a problem for Apple since they're designing huge SoCs with a lot of other high pincount, high speed I/O. (And high performance power delivery, which also requires a ton of pins.)

PCIe's bandwidth per pin is massively higher than ONFI/Toggle, so Apple designed tiny lightweight PCIe-to-NAND bridge chips. Each one provides several NAND channels, and typically lives inside the same package as the NAND die it serves. The interface from this bridge to Apple's NVMe controller is a x1 PCIe link.

Base M-series chips have four x1 links for flash memory, Pro/Max chips have eight. As far as I know these PCIe lanes are not capable of being used for anything else, they're plumbed only to the NVMe controller.