Why is TDP the same on all the nMP CPUs?

Discussion in 'Mac Pro' started by propower, Dec 22, 2013.

  1. propower macrumors 6502a

    Joined:
    Jul 23, 2010
    #1
    No horse in the race - just geek curious....

    From AnandTech articles and others it seems the IB Xeon V2 chips are based on one of three die sizes 6c, 10c, and 12c. at least this is clear about the 2600 series. But I can find no die size info on the 1600 V2 series. They are all 22nm processes...

    Simple question:
    Can anyone point to a source for the die sizes of the
    E51620 V2, E51650 V2 and E51680 V2?
    From Wikipedia link the 12c may be process IB EP10 (346mm^2) but it is not 100% clear

    Follow on question:
    If the 8c and 12c are on significantly larger die - why doesn't the TDP scale with this?

    http://www.anandtech.com/show/7285/intel-xeon-e5-2600-v2-12-core-ivy-bridge-ep/5

    http://en.wikipedia.org/wiki/List_of_Intel_Xeon_microprocessors
     
  2. deconstruct60 macrumors 604

    Joined:
    Mar 10, 2009
    #2
    TDP is a design constraint. It isn't necessarily a consumption measurement. Lower workloads or proactively underclocking a bit and will always operate under that limit.

    if there are 8 chips with the same TDP , pin outs , and chipset support requirements then they can all be dropped into the same design.


    Die size isn't necessary correlated with power consumption at you are making it out to be. Two factors. One, it depends upon what what are adding and if it is linearly consuming as much power. Second, part of this is dissipation by the whole chip package, not the die that occupies a subset of space inside.

    The 8c and 12c don't clock as high in normal mode and only do clock as high as 4-6c models when only using that many cores.

    The chip package can spread out the heat. smaller die has a bigger ratio of spreading than the larger die. they both can crank out the same amount of power to be transferred to the same spread area.
     
  3. ZnU macrumors regular

    Joined:
    May 24, 2006
    #3
    From this Apple support document, the chips clearly do have different power consumption at max load. You can't back out absolute numbers because that's total system power consumption, but the 12-core draws a full 65W more than the 4-core.
     
  4. propower, Dec 23, 2013
    Last edited: Dec 23, 2013

    propower thread starter macrumors 6502a

    Joined:
    Jul 23, 2010
    #4
    - Not quite where I was heading :)... I used to design Hybrid Power supplies (Hybrids in this use refers to Power Supplies made with with unpackaged die). In that world Power Handling (max power) of a die is directly correlated with die size and thermal resistance (the thermal path to whatever the known "sink" is). There really was no power limit but instead a thermal limit. Keep the Tj below "x" degrees C and it will be fine.

    So... assuming the current 4 and 6 core CPUs are on the "6c die" from the Anandtech article and the 8 core is on the 10c die (which is at the heart of my original question) I was pondering why the "larger one" wasn't able to handle more power due to its larger die size and consequent lower thermal resistance. IME for large dies like these the spreading angle will be very similar and any area added will be proportional to the die size -- meaning both die will see a proportional increase in effective area but the larger part would still be proportionally larger with a consequent lower thermal resistance (my best info so far suggests 256mm^2 for 6c die IvyB EP6 and with 347mm^2 on 8c IvyB EP-10 (wikipedia link)
     
  5. ZnU macrumors regular

    Joined:
    May 24, 2006
    #5
    Again, those numbers, as I read the document anyway, are for total system power consumption under max CPU load, not for the power consumption of the CPU models in particular.
     
  6. propower thread starter macrumors 6502a

    Joined:
    Jul 23, 2010
    #6
    Oops - my bad - amending post - Thanks
     

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