M4? The name is just marketing. It could be something different than M3 with a "better neural engine" but they may call it M3X or M3 AI+ or whatever they want to, if they're not ready to start the M4 generation yet.
This is a more insightful comment than might appear.
While I am often skeptical of Gurman's claims, this is not perhaps as crazy as it sounds.
You may be aware of the recently released Apple Optimization Guide:
https://developer.apple.com/download/apple-silicon-cpu-optimization-guide/
There's nothing especially surprising there, mostly confirms (with vastly less detail) the work already published by myself and Dougall Johnson.
BUT
There is one strange, almost unreal, aspect to it in that talks about and gives numbers for the A14, 15, 16 and M1, 2, 3; but it does not talk about the A17. The general conclusion was that A14 -> M1, A15->M2, A17->M3, and A16 was mostly just a hiccup, a kinda of slightly tweaked an optimized A16.
This conclusion may have been incorrect in two senses: that we have assumed a fairly obvious lockstep between A chips and M chips, and that we assumed the M3 was "locked" to the A17.
If one wants to play devils advocate, one can make a number of hypotheses:
(a) The SoCs consist of many IP blocks, and these could be independently modified on different Designs. In other words, the M3 may pick up the (trailing) CPU from the A16 AND the (leading) GPU from the A17. Or the equivalent for the ISP, the media blocks, the ANE, etc.
(b) One thing Apple seems to do (as a fast mover that doesn't want to slip schedule; nVidia BTW does the same thing and have even discussed it publicly to a very small extent) is ship "experimental" versions of certain features on a chip without seriously expecting that they will work 100%. They're there to provide a hardware debugging platform, or for the OS/driver people to start ramping things up, but are hidden behind chicken bits that switch them off for users.
You could imagine an even more aggressive version of this idea, where new functionality is prototyped in A, then M, then M Pro, then M Max; each new set of masks gives you another chance to fix bugs and make small tweaks based on what you learned earlier.
This sort of thing is possible IF (unlike a certain CPU company named I***l, you are able to **** about new functionality until you are 100% certain you have it working and ready to ship...)
Given both these factors, you could imagine a world where, each year, there's some degree of flexibility in M vs A scheduling. The M4 could, for example, include ANE improvements that were prototyped in the A17 (but not activated) and have now, six months later, had the last few hardware bugs fixed in the M4 silicon, and are ready for use.
This may also (to some extent) hook into the missing(?) M3 Ultra.
If you go by the Apple patents then over the past few years Apple have done a lot of work to support the very high end. This is functionality to speed up virtualization, to support a variety of page types (and thus both large pages for Apple use, and alternative OS support), and a new cache protocol to support substantially growing the number of cores and other IP blocks. But we've seen none of this in products.
This could be patents that go nowhere (there are definitely *some* of those, though not many); but my guess is this is tough functionality to get right, so it's been iterated and debugged one mask set at a time, and, again if this is now ready, it may make sense for Apple to make a splash with a set of high-end "M4" products that are not just what we'd expect from an M3 Ultra, but ready to take on one or both of large AMD and large nVidia systems (enough cores, enough memory, enough HPC/server functionality).
Likewise the somewhat disappointing (ie basically none-existent) IPC bump for the M3, even though it definitely has 9-wide (rather than 8-wide) functionality, and probably has somewhat boosted branch prediction – again the most aggressive aspects of the new designs may have been hidden behind chicken bits, being debugged in A17 and M3, and are now ready for actual customer use in a May release M4?
Finally there is the simple issue of TSMC economics. We all know the story of N3B vs N3E. It makes no sense (for Apple or TSMC) to stick with N3B if N3E is materially better (faster, cheaper, or higher yield). So might as well spin out an "M4" that's, in some sense a bug-fixed M3, but which is cheaper to manufacture, and maybe also helps somewhat realign the roadmaps, so that maybe the A19 and M5 ship on the expected schedule in 2025?
Or maybe we switch to a permanent case of M running a few months before A, because, ultimately, a schedule slip in M doesn't affect anything, whereas a schedule slip in A would be a disaster – so M a few months before A acts as a chance to get everything lined up and tested before A? AND it's a lot easier to debug and perfect the new features of the new iPhone if you have essentially the equivalent of that A chip available in a Mac...