Does anyone know (On average) how many (usable) chips that that are likely to get per wafer?
5 nm is on 300 mm ("12 inch") wafers, so there is a hell of a lot of surface area available, and I've found an Anandtech report showing 2600 good die on a test wafer, with 600 failed die and some number of edge die (die at the edge fo the wafer are generally discarded as a quality protection against field returns.
I would assume that TSMC would not release a die to production with less than 90-955 yield, so, being teh lazt mathematics engineer that I am, I would expect 3000 good die per wafer.
www anandtech com /show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020
This needs a major caveat: the test die that was referenced by Anandtech could be either smaller or larger than an Apple-designed die, so the good die per wafer yield is still very much up in the air. WHere I work, and given our technology node, we can get 25,000 die printed on a 15 mm ("6 inch") wafer. For our more modern devices, it's more like 25,000 on a 200 mm ("8 inch") wafer. But our die are relatively small, so I would't expect that an Apple Axxx would fit that many die, even on a 300 mm wafer.
(Yes, I am a semiconductor manufacturing engineer, so my comments on edge die and yield expectations are generally valid, but I really don't have any secret insight into TSMC's process for Apple Axxx ships. So my insight is not worth much more than Livverpool's "Depends, we talking chocolate, vanilla or strawberry wafers? ??".)