Remember when Intel tried to secure some capacity or an earlier process...and then couldn't design a chip to run on their fab?
Errr. Not really what happened. Intel had problems getting Xeon SP4 running on their own fab ( went through
" ...
With a total of 12 (!) steppings, they haven’t exactly covered themselves with glory either, and I can’t remember any project so far that needed so many steppings before you could even use it to some extent. ..."
Intel’s new Xeons, i.e. the scalable server processors of the 4th generation, are delayed again. Once again, one might say, and the reasons are very diverse. The problems and errors are collected…
www.igorslab.de
Intel had a phase were they were trying multiple strategies all at the same time. They diluted their focus too broad ( sometimes too much cash leads to too many projects. ) and lots of projects slid into longer delays. The particular fab process was the primary factor. The only coupled factor there was that Intel was shifting to using more 'open' design tools ( and less 100% internal custom stuff). That really didn't just apply to TSMC; design to their own future fab processes was linked to that also.
Making several product lines very chunky chiplets and pour "3D" construction ( EMIB & Foveros ) on several packages didn't speed things up in the short-to-intermediate term.
Intel has also 'flip flopped' a bit on exclusively doing Arrow Lake on TSMC N3B. There are reportedly Intel 20A alterantives f
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In the case of Core Ultra 5 240F, a change of CPU tiles may also mean a change of fabrication node. The 6+8 version is said to be using Intel 20A, while the 8+16 is rumored to use either Intel 20A or TSMC 3 nm node. ..."
Core Ultra 5 240F, expected to use two versions of the Arrow Lake-S silicon A new rumor suggests Intel will continue its ‘tradition’ to mix silicon dies within the mid-range CPU segment. The next-gen Arrow Lake-S series is on track to debut on the desktop platform this year, introducing the...
videocardz.com
Lunar Lake (which is also a Ultra 200 series variant) is also deeply committed to TSMC N3B so there is more than a decent chance there is a N3B 'CPU+GPU' variant tile there also. So decent chance some 'overhead' here is the time to do the double design work (not can't design for TSMC N3. The GPU stuff was always on a TSMC track . So the notion that Intel had no skill set exposure there is dubious. )
[ Intel doing Lion Cove / Skymount on two different fab processes is expensive ( not going to help Intel's short term margins). But it likely will the an insightful "learn" process ( paying for an expensive education. ) . The other problem is Intel just can't make enough volume EUV wafer to do 'everything' in-house. ]
Back in 2023
Intel is slightly adjusting its Arrow Lake rollout as it looks to cut costs and navigate weakened demand.
www.tomshardware.com
There has been reports that tried to couple "14th gen" Meteor Lake's GPU tile to 3nm , but those are clearly not correct at this point ( It has shipped without and isn't classified "14th gen" ).
And if Meteor Lake doesn't come out "on time" it was going to be very hard for Arrow Lake (the follow on) to do launch on time also.
Whether Launch means "shipping in Q3 also" is a bit up in the air:
Core Ultra 200V “Lunar Lake” arrives next quarter The first Lion Cove and Skymont-based CPU series coming soon, also the first Xe2 based product. Intel is sharing new details about its upcoming client architecture, Lunar Lake, aiming to compete with today’s Microsoft’s and Qualcomm’s next-gen...
videocardz.com
but since the lead time on "baking" N3B chips is relatively long there is likely already in production. Even if wanted them in Q4 would need to have started now to have any substantive quantities by then.
Who else can even bid on this and be ready to go? Samsung? AMD? Amazon or Google?
MediaTek launched on TSMC N4 before Apple did. Samsung has their own S3 process to shepard.
If not blocked, Huawei probably would be (the used to be first in line with Apple until they were restricted).
AmpereComputing just announced they are ready to go.
" James and Wittich also both highlighted the company’s upcoming new AmpereOne® platform by announcing a 12-channel 256 core CPU is ready to go on the N3 process node. ..."
Ampere Computing® today released its annual update on upcoming products and milestones, highlighting the company’s continued innovation and invention around sustainable, power efficient computing for the Cloud and AI. The company also announced that they are working with Qualcomm on a joint...
amperecomputing.com
AMD appears to be going for "quantity" over "density" so the Zen 5 TSMC N4 variants are going to be the 2024 production targets. If pressed AMD could have tried , but they can still take share away from Intel with N4 variants so that is a safer route for them. And it looks like although AmpereOne is ready to go they are not going to ship a large quantity of the N3 variant this calendar year. AMD may have pick some speciality chiplet for early N2 though ( as competition in AI/ML is only going to get tougher in 2024-245).
Arm's "ready to go" Neoverse CSS chiplets might be ready for some TSMC N3 variant by end of year.
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Finally, underscoring the quick turnaround times that Arm is envisioning with the V3 CSS IP, the company is already announcing a design win with Socionext, who is designing a 32 core V3 CSS chiplet to be fabbed at TSMC. ..."
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It wouldn't be surprising if that 'waited' until N3P was in production though. That would bring along Amazon and Google since they are leveraging Arm Neoverse ecosystem. Arm has a working relationship with TSMC to cooperatively develop Arm chiplets going forward. Arm doesn't put in the wafer orders but being 'ready' for orders is more layered on Arm.