Ah.
Well, using Opteron as an example - a bunch of us came up with the concept on a napkin at a fancy french restaurant. Then we write a behavioral simulator in a language like Verilog. This simulates things at a very high level - for example, to simulate an adder we essentially just say "A=B+C." In Opteron's case I wrote some of the verilog to convert things to 64-bit, in the process inventing some of the instruction set.
Then, verilog in hand, we start breaking things into blocks, and figure out more or less what types of circuits would be in each block, and where, physically, the blocks would be on the chip and how big they would likely be. There are two types of blocks - macroblocks and standard cell blocks. Macroblocks are designed transistor-by-transistor. Standard cell block are designed at a slightly higher level, using gates (like "NAND," "NOR," etc.). The designers manually translate the verilog into gates and/or transistors (at AMD, at least. Most places, like nVidia, use a synthesis tool to automatically do this, but the results suck). We manually position the gates, and draw the transistors in the macroblocks.
We then use "formal verification" to make sure that the resulting logic is mathematically identical to the behavioral verilog.
The behavioral verilog, by the way, is executed against a large suite of test patterns using a large collection of x86 computers (many thousand machines, including all of our desktop workstations plus rack machines) 24 hours a day, and any anomalies generate an alert
