Their absolute bleeding edge will not be manufactured outside Taiwan anytime soon. They benefit greatly from the concentration of R&D and engineering capabilities as well as cheap labor in Taiwan. They have already said that e.g. the Arizona fab will not focus on consumer products like Apple's, but on semiconductors related to national security and critical infrastructure, which are usually one or two generations behind the leading edge.
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Apple Supplier TSMC Readies 2nm Chips for 2024
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The thing is these naming schemes aren't really connected to physical characteristics any more, they're just marketing speak.
And only until Black Friday when everyone will want an 85" 8k television for $250.
And when China wants a piece of that pie and takes it by force specifically because they know it’ll hurt American industries? What’s Apple’s plan then…?
It's not like they aren't working with mainland China now ...
A few years ago I read an article in which it said that you can't go smaller than 2nm. Seems not to be the case then.
It’s certainly not the case. That said, nothing will be 2nm in size on this process.
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Because this keeps the US vested in the defence of Taiwan. It’s why they always build their leading edge fabs there (well that and their skilled workforce).
I’m a TSMC shareholder and this is very good news, keeps them at the forefront and will likely be their first GAA process. No doubt Apple will have priority access to these chips as usual.
It’s nothing but a naming scheme, N2 like N5 or N5P. The transistors are probably more like 20nm in size with many different ways to measure, height, width, distance between etc. The best way to judge how advanced a lithography node is, is to look at transistor densities.
I don't think Intel's processors will actually be smaller than 1 nm. Intel has maintained that their 10 nm processors hsve performance/watt equivalent to 7 nm. To that end, Intel has renamed their fab process to a number that indicates performance/watt equivalent to industry standard process.Intel PR desk front-running TSMC...
"But Intel's prospects are more interesting as we look ahead to 2024, when the company expects to finalize the design for its first chips with transistors smaller than 1 nanometer. They'll be measured by angstroms, instead."
Intel's revised roadmap looks beyond 1 nanometer chips
Forget about "SuperFin Enhanced," the previous name for the node powering Intel's upcoming 10nm Alder Lake processors. Now, that node is just called "Intel 7," according to the company's revised roadmap.www.engadget.com
For instance, Intel 7 process due on the 2nd half of this year is actually 10 nm, but with the performance characteristics of 7 nm. From what I can gather, Intel 20A is 5 nm.
To be fair to Intel, it did announce that it expects its 20A (20 angstrom aka 2nm) node to be ready in 2024 as well. Also, Intel announced it’s planning to move on from FinFet and move to RibbonFet. The key thing for Intel is to execute. TSMC has a proven track record in the past few years, Intel does not. Either way, 2025 CPU products are going to be amazing. And we consumers will win.
TSMC is one of the main reasons why Taiwan has not been invaded by the People’s Liberation Army.
The best way is to look at minimum area, minimum spacing, and minimum width. Not sure what “transistor densities” is supposed to mean or why everyone keeps talking about it. I never once talked about “transistor density” when I was designing CPUs. The “transistor density” is up to the designer, who decides how close together to stick transistors - the minimum allowable spacing is seldom a good idea.
You should stop believing what the marketing crap says. 2nm doesn't mean anything more than one feature will be 2nm.
Transistor density is what matters.
The density is decided by the process design rules. The number of tracks in a library along with the number of metal layers will determine the gate spacing and hence the transistor density.
Backend design does not place any transistors today. TSMC along with ARM and others have libraries of gates along with memory compilers.
You don't get to decide gate spacing either.
If you use a custom library you use the transistor design rules for whatever process it is.
So for silicon processes the best way to compare is transistor density. The basic assumption is 6 or 7 transistors per flop.
It’s just another simplified way for consumers to compare technologies. The fact that densities vary based on the type of functional unit (e.g. CPUs vs. GPUs vs. RAM) doesn’t enter into the comparison which makes it about as accurate as specifying nm. Intel tried to use it a few years ago but gave it up.
Don’t worry, it only takes a tornado to fix their droughts
