I can't wait to get my hands on an a machine with an M5 so I can imprint my memory engrams on it. "The torrential flood of illogic would be most entertaining."
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Apple Supplier TSMC Readies 2nm Chips for 2024
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There's are many reasons why TSMC's process is far superior to the competition and it's not related to the density. Ultimately you only care about PPA. For example, TSMC's 3nm node has some cutting edge features that Intel has never been able to crack despite many years of trying and failing. Only people who have worked with this node will know exactly what I'm talking about as this is not public info.
The problem for intel is that we believe TSMC when they say they're going to do this.
There is a huge difference between tsmc’s cell library and the cells we created ourselves (and even more of a difference when you look at our custom circuits). And we put in bypass caps everywhere. So what are you really comparing? I could have squeezed many more transistor together and met the design rules, but that wouldn’t have been a useful device. A ram has different density than an adder. Why create a fake metric when the real metrics - minimum area, minimum spacing (or pitch), and minimum width, are readily available? And when I look at those, TSMC 5 is way ahead of Intel 10, and approximately equal to Intel 7.
Which is why only PPA maters to real engineers. Process node naming is more marketing for the public these days. Every new process node presentation will give some estimated metrics but everyone runs their own test RLM's through the early PDK's to collect relevant info. The impact of a new process node affects every design in different ways. Density is only one of many contributors to PPA improvements. TSMC's libraries never push the design rule limits, as compared to other vendors, because they are optimized for yield. As a fab they have to be conservative to ensure no issues for a wide variety of designs.
TSMC wants to eradicate the nanometer completely and aims for zero nanometer in 2026.
So much for Intel’s “parity in 2024” with 20Å (AKA renamed Intel 5nm).
But 20Å is more fun to write than 2nm
But 20Å is more fun to write than 2nm
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Getting the (Chinese PLA) army across water (to Taiwan) is difficult. Holding it (Taiwan) against US (aircraft carrier) naval supremacy is even more difficult. Think Falklands.
The Chinese will know this and are unlikely to try. Supporting this, China has recently slowed its aircraft carrier building plans.
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The terms names they use (7nm, 5nm, 2nm) aren't actually indicative of an actual measurement anymore. It's much too complicated to pair it down to one number. Those are more like marketing terms now than actual measurements. There are a lot of optimizations they can still do and probably have another good 15 years of improvements they can make. In that same vain, Intels 10nm is pretty much equivalent to TSMC's 7nm when it comes to actual transistor density.
I don’t recall any US President ever bringing into question their defensive commitments to Taiwan — not even Trump when he was rattling the cages of other allies for seemingly no apparent reason. For China’s part,
I think they know attacking Taiwan would be a net negative for them (tons of regional instability, etc.). Those resources would be much better spent continuing to grow their own economic base.
Ohhh.... again, people stuck in the past decade with dreams of a full day battery life.
My iPhone takes me easy to 2 days (1.5 days heavy use) but I drop it on a £7 wireless charger every evening before sleep and never once wished it had a better battery life. Not an issue for me.
There has always been a lot of drama around here when it comes to battery life. It is freaking hilarious
I'm not an expert on this stuff, so I'll point to this comment thread on anandtech:
https://forums.anandtech.com/threads/why-intel-14nm-was-named-14nm.2488581/
Basically, it's a historical reference to Moore's law. Every subsequent process name represents something like a doubling of transistor density. Historically that correlated with a transistor's size (or certain features of a transistor like gate length) but new technologies allowed companies to increase transistor density without a corresponding decrease in transistor size. And so the process size naming continued with the reference to Moore's law without the connection to an actual transistor feature size.
But transistor density is a better metric than saying Xnm process is better than Ynm process.
It's not a fake metric. When I'm running synthesis for a design and doing library and process evaluation (part of my job) I look at PPA and part of that is density. And yes rules for memories are different but I'm also using memory compilers for the size memories I want.
Ultimate it boils down to PPA (power performance area) like another poster said.
The other issue is even within a specific process node you will have different libraries with different sizes and tracks. Even HVT and RVT libraries in the same process have different cell area.
I think the best benchmark would be a standardized design that has memories, maybe a RISC 5 cluster with some sort of interconnect, etc. Let's see what that looks like in layout at a particular frequency.
Everything else to do with naming is hype and hyperbole. 2nm, 5nm and all the rest mean nothing but marketing speak.
Maybe a single metric is not enough... it really depends on the chips that you are designing and their operating conditions.
Exactly, which is why i say “give me the design rules.” That’s always how I evaluated a process. Any particular metric may seem “worse,” but if, say, the M0 thickness is higher in one process vs another, I can adapt by spreading the wires farther apart, which I can compensate for by changing the standard cell aspect ratio, which I can compensate for by adjusting the power grid spacing, etc. etc. Everything is trade offs. But ”density” tells me nothing unless you are limiting your comparison to the cell libraries and design kits provided by each fab (which, I can assure you, Apple, AMD, Intel, etc. do not do).
It's more common to see congestion problems with the BEOL instead of FEOL. There's usually plenty of placement sites available because the limitation is the pin escapes and routing resources for clock, power, and signal. Unfortunately BEOL has not scaled like FEOL. For logic heavy blocks in a CPU (ie LS, EX, etc) the various metal stack options will impact your design optimization as much as, if not more, than scaling of the base layers. You will get some base layer advantages in memory dominated blocks (ie BP). GPU designs are optimized with more resources in the lower metals while CPU is better off with more Mz layers. Intel's previous advantage was having a custom process optimized for the specific CPU projects. An optimized (previously cutting edge) process was the key to their domination of the industry. Ideally you want an optimized process for each design which is impossible for monolithic SOC projects so you have to compromise. Now that we're moving to chiplets we have to option to select the best process for the job. In the next decade the packaging innovations will be the driver of forward progress.
I’m happy for you. But it probably just means you don’t use your phone as much as other people do.Ohhh.... again, people stuck in the past decade with dreams of a full day battery life.
My iPhone takes me easy to 2 days (1.5 days heavy use) but I drop it on a £7 wireless charger every evening before sleep and never once wished it had a better battery life. Not an issue for me.
There has always been a lot of drama around here when it comes to battery life. It is freaking hilarious
With the battery draining 14.6/7, my 12 Pro Max only gets me a little past dinner with heavy use. I miss my 11 Pro Max for this reason. This year’s phones should have increased battery life.
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For China SMIC is on 7 and 14 nm nodes. Huawei’s HiSilicon branch, which is a chip design company, is leading the world in chip design in a few areas like 5G modern SOC (better than Qualcomm), and top notch in mobile processor IC design (not too much behind Apple). Just 2 examples among many. I don’t know why you think China is more than 15 years behind Taiwan.
Huawei’s processor designs are nowhere close to Apple. What are you talking about?
Also, SMIC’s 7nm node is not even caught up to TSMC’s 7nm node, which TSMC has had for years.
Depends how you define "design." Hisilicon's latest and greatest Kirin 9000 application processor and GPU (Mali) was *designed* by Arm while other parts of the SOC engineering and IP portfolio was provided by their ASIC vendor. In fact the assembly of the SOC could have been completely outsourced to an ASIC vendor as many big tech companies do. In reality there are very few talented architects and designers in the industry that actually move the needle forward. They are extremely well compensated and concentrated in a small number of tier 1 US based companies. They would never work for tier 2 US companies and sure as heck would not be working for HiSilicon. Even Intel is having a great deal of trouble attracting decent talent. You simply won't be "leading the world in chip design" without the best talent. Using an analogy think about the difficulty people have trying to build a top notch NBA team without the ability to recruit the handful of star players.