A Pro Display XDR without DSC would essentially render every other part of an intermediate Thunderbolt device useless
True, XDR uses at least 36.6 Gbps without DSC. That affects write speeds (only 3 Gbps remaining, but probably less) but doesn't affect read speed much.
however, I can't see why a 2-port device couldn't simply pass through the packets. It might require a Titan Ridge vs. an Alpine Ridge controller though.
Maybe the trick Apple uses to force two four lane HBR3 connections doesn't work with an intermediate Thunderbolt device or would require extra work?
Alpine Ridge is capable of passing HBR3 packets from a Titan Ridge or later host to a downstream Titan Ridge or later device to convert to DisplayPort 1.4, so I don't think that's the issue.
When the Pro Display XDR is being driven via a GPU that supports HBR3 but not DSC, it obviously requires more bandwidth than a single x4 DisplayPort main link can provide. A Thunderbolt 3 link can't tunnel two full x4 HBR3 main links, however, it can carry one x4 and one x2 main link. This struck me as more likely to be what the Pro Display XDR actually does—multi-link SST using 6 lanes of HBR3 rather than 8. Even if you do the math to factor in the overhead it all checks out, and Thunderbolt controllers do support flexible main link widths (x1, x2, x4) on all of their DisplayPort interfaces and protocol adapters. Is what AGDCDiagnose is showing indicative of physical or logical connections? For instance, Thunderbolt PCIe link rates are all represented as Gen 1 internally despite actual throughput.
For other people reading along, the Gen 1 (2.5 GT/s) link rates you mention are for the internal PCIe devices of a Thunderbolt controller (downstream bridges, NHI Thunderbolt controller, XHCI USB controller, and Thunderbolt ports). The external PCIe connections (the upstream of a host controller to connect to PCIe buss of host and the downstream of a peripheral controller to connect downstream PCIe devices of the dock) report the correct PCIe link rates. The upstream of the integrated Thunderbolt controller of Ice Lake also reports as gen 1, since the Ice Lake Thunderbolt controller is internal to the CPU. The integrated Thunderbolt controller of M1 is an ARM device, not PCIe - each controller is a separate PCIe bus (multiple devices can use the same bus number if they are not connected to the same Thunderbolt port of the M1 - I would like to see a screenshot of the PCI tab of System Information.app with two Thunderbolt devices connected).
The AGDCDiagnose output shows info from the GPU so it is showing info for physical connections since the GPU is physically connected to the Thunderbolt controller DisplayPort inputs (DisplayPort In Adapters). People have shown the XDR uses two four lane HBR3 connections when DSC is not used. Thunderbolt can transmit two HBR3 connections for 6K 60Hz because 6K 60Hz does not use all the bandwidth of dual HBR3 and Thunderbolt does not transmit the DisplayPort stuffing symbols used to fill the DisplayPort bandwidth.
You can test this stuffing symbol theory - connect two 4K 60Hz displays. They both use four lanes of HBR2 (34.56 Gbps). Measure the write speed to a NVMe or eGPU connected to the same Thunderbolt port. Then change the timing of the displays to 2560x1440 60Hz (low resolution/not scaled). The connections are still dual four lane HBR2, but the write speed should now be greater.
There are various rules for how Thunderbolt 4 and USB4 device topologies work. Most notably, once a Thunderbolt 3 link is established, all the downstream links below that link are prohibited from being USB4 links. Also, a downstream Thunderbolt connection cannot be established unless the host router and connection manager also support Thunderbolt. There's more info in
this presentation.
That's interesting. So tunnelled USB3 cannot pass through a Thunderbolt device according to that document. It's not explicitly stated though. I suppose the intent (or one of the outcomes) is to have a non-broken USB4 topology (tree structure) so that the USB3 topology matches. This means you can see the USB hubs connected to a USB3 controller in the USB tab of System Information.app and that tree will match the tree of USB4 devices (whenever USB4 devices start to exist - I haven't seen any yet). The trees won't match if you added Thunderbolt peripherals in the mix.
PCIe topology matches Thunderbolt/USB4 topology (there is a close relationship).
DisplayPort topology: Thunderbolt/USB4 does not pretend to be a tree of DisplayPort MST hubs. Thunderbolt has more bandwidth than DisplayPort, and can transmit more than one full DisplayPort SST signal. Trying to fake an MST topology would be too limiting.
USB topology: for tunnelling USB3, if USB4 pretends to be a series of USB3 hubs, then that limits itself to one tunnelled USB3 stream at the host so all USB4 devices would share that USB3 bandwidth (usually 10 Gbps). The PCIe tunnelling to an XHCI controller method used by Thunderbolt is superior because Thunderbolt has ≈22 Gbps of PCIe bandwidth to use.
That document seems to suggest that once a Thunderbolt link exists (10.3125 or 20.625 Gbps per lane) all downstream links must be Thunderbolt links. i.e. you cannot connect a USB4 device and have its downstream links use USB4 links - 10 or 20 Gbps per lane.
That document also suggests that you cannot use a USB4 dock to connect a Thunderbolt dock to a USB4 host that doesn't support Thunderbolt link rates even though the link between the host and the USB4 dock is USB4?
I think perhaps the reason you weren't seeing the USB protocol adapters in the OWC Thunderbolt Hub was because it wasn't connected to a Thunderbolt 4/USB4 host, at least if you're referring to the thread I was looking at the other day.
I guess we need to see what it looks like when connected to an M1 Mac. Just need someone to provide the ioreg output. Even then it may not show USB3 protocol adapters if it prefers PCIe tunnelling. In that case, we need a USB4 host that doesn't support PCIe tunnelling (do any exist yet?). One thing disappointing about the OWC Thunderbolt hub the way it's implemented is that all the Thunderbolt ports share the same USB3 bandwidth so the total USB3 bandwidth cannot exceed 10 Gbps - need to double check that by connecting USB devices - but the existence of the four/five port hubs is probably sufficient evidence of that. Why didn't Intel implement a 5 port USB controller in the Goshen Ridge instead of the two port controller? Is the hub required for USB4 functionality (if it has USB4 functionality)? I guess there needs to be a hub for USB-C functionality - but when connected via Thunderbolt, it could switch from hub mode to controller mode.
As can the Samsung T7, which the the person you were responding to already has. However, USB 3.2 Gen 2x2 SSDs / enclosures (which are also readily available) can do 2000 MB/s in conjunction with an appropriate host, should you happen to find one.
Just put a USB 3.2 gen 2x2 card in a Thunderbolt 3 PCIe expansion box. I don't know if macOS supports gen 2x2 though.
