Agreed-I'd say:i_b_joshua said:
PM G5 1.8GHz-2x 250GB Sata RAID (many PC's have a RAID SATA config), 512MB (exp. to 8GB),FX5900
PM G5 2.2GHz-2x 250GB Sata RAID (many PC's have a RAID SATA config), 1GB(exp. to 8GB),FX6800 or 9800
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Clearing out G5s?
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PM G5 1.8GHz-2x 250GB Sata RAID (many PC's have a RAID SATA config), 512MB (exp. to 8GB),FX5900
PM G5 2.2GHz-2x 250GB Sata RAID (many PC's have a RAID SATA config), 1GB(exp. to 8GB),FX6800 or 9800
G5-Tower
iMac-sphere, perhaps a ULV G5 (970FX)
Cub-Shuttle XPC's are great compact 'cubes'-Apple should have a SFF PC
iMac-sphere, perhaps a ULV G5 (970FX)
Cub-Shuttle XPC's are great compact 'cubes'-Apple should have a SFF PC
fpnc said:
Then you really don't understand how either HyperTransport or the Apple FSB work, since both are basically the same thing. The G5 motherboards use unidirectional channels - one up, one down - to the rest of the system, and each channel is half of the clockrate of the processor. This, in efffect, is an awful lot like having a bus that's the combined frequencies with some strengths and weaknesses, the most obvious of which being that you can write and read at the same time, but are doing so at 800-1000mhz instead of outright 1.6-2.0ghz. This is also how Apple deals with the memory bus, since the RAM is both reading and writing on the edges of the clock cycle, pulling data and putting it back without the need to dedicate three cycles - fetch, operate, store - as would traditionally be the case.
johnnowak said:
That's not a bad idea. At least they were quiet!
How many of you think the new G5s will be liquid-cooled?
Folks, as much as we love the Cube and wish new G5 cubes were here, this topic is not about the cubes AND it's highly unlikely anything cube related will ever happen again.
Calebj14 said:
AAAHHHHH! Godd*mnit please dont start this cube talk here too. Im practically about to shoot from having it infect the other threads, please dont let it happen here too!
thatwendigo said:
Hey man, spend as much time as you possibly can with your brother because trust me, I know how that is. And also I dont even know if my previous post is worth responding to, Id rather you spend your time with your family.
MacGizmo said:GOD I hate knowing what I know...
Have a little faith, and don't believe everything you read.
That is all.
PS: Not speaking for my employer.
DO YOU WORK FOR NEATGEKKO!?
MacGizmo said:GOD I hate knowing what I know...
Have a little faith, and don't believe everything you read.
That is all.
PS: Not speaking for my employer.
I took it as he worked for Apple.
Calebj14 said:
I know. Im just having a little inside fun.
You had to be around similar threads a few months ago to understand the power of the Neatgekko.
sushi said:Neatgekko --> Awesome power!
Sushi
Yeah, he/she is probably under a new guise... probably a "regular" poster by now...
Hey Sushi your a "regular" poster...
No offence, just having a bad week (and its only Monday)...
Where the $^&# is my PB...
In response to my earlier posts the following comments were made:
Well, I think you two "experts" need to get together since you both seem to want to correct my "errors" but you're basically saying the opposite to one another.
As I've said before, I don't think you can directly compare the FSB designs between the Athlon 64 and the Power Mac G5. That's probably why the two of you (thatwendigo and AidenShaw) seem to disagree on what the FSB is on the Athlon 64 (is it the memory interface or is it the system bus?). I think in the more traditional sense it is really what is called the system bus and AMD calls the Athlon 64's HyperTransport link the system bus. And certainly, the 1GHz bus that runs between the G5 and the Power Mac's system controller is both the system bus AND the FSB.
As far as what a FSB is, here is one definition I found in an article that was published on TechNewsWorld.com
"As one of the most important processing channels, the frontside bus is the primary interface that connects a microprocessor to other system devices. Typically, the FSB allows the processor to communicate with main memory (RAM), the system chipset, PCI devices, the graphics card and other peripheral buses."
While this definition fits well on the Power Mac G5 you can see that the design of the Athlon 64 doesn't really fit here. And that's always been my point (which thatwendigo seems to want to disagree with).
Interestingly, this article then goes on to discuss the various differences in the methods that Intel, AMD, and IBM (G5) are pursuing to break what they termed the "Frontside Bus Bottleneck." Hint, although there are similarities it's apparent that IBM and AMD are not pursuing the same track.
Here is the link:
http://www.technewsworld.com/story/31594.html
Or how about this (from Geek.com):
"Front Side Bus (FSB) - The speed of the bus connecting the microprocessor, its chipset, and connected main memory. In architectures where the processor interacts directly with main memory, the definition of a singular front side bus is less clear. In such a case you would have to specify two FSB speeds, one for the connection to main memory and one for the connection to the processor chipset."
Which really, I guess, directly supports my position about trying to compare the Athlon 64 "FSB" to the Power Mac G5.
Well, since Arstech specifically asked about the available bus multipliers when they interviewed IBM's Peter Sandon (chief architect on the PPC970) I think that probably indicates that at least some people think that bus multipliers other than 2X are potentially useful. When I went back to this article I found that Peter Sandon said that the "processor design" supports bus multipliers of 2, 3, 4, and 6. However, I think it was unclear whether the PPC970 actually implemented those multipliers (i.e. the design could support them, but it may not be implemented in the 970).
Here is the link where they discuss the bus multipliers:
http://arstechnica.com/cpu/03q2/ppc970-interview/ppc970-interview-2.html
Well, I guess I rest my case (or arguments).
thatwendigo said:
AidenShaw said:
Well, I think you two "experts" need to get together since you both seem to want to correct my "errors" but you're basically saying the opposite to one another.
As I've said before, I don't think you can directly compare the FSB designs between the Athlon 64 and the Power Mac G5. That's probably why the two of you (thatwendigo and AidenShaw) seem to disagree on what the FSB is on the Athlon 64 (is it the memory interface or is it the system bus?). I think in the more traditional sense it is really what is called the system bus and AMD calls the Athlon 64's HyperTransport link the system bus. And certainly, the 1GHz bus that runs between the G5 and the Power Mac's system controller is both the system bus AND the FSB.
As far as what a FSB is, here is one definition I found in an article that was published on TechNewsWorld.com
"As one of the most important processing channels, the frontside bus is the primary interface that connects a microprocessor to other system devices. Typically, the FSB allows the processor to communicate with main memory (RAM), the system chipset, PCI devices, the graphics card and other peripheral buses."
While this definition fits well on the Power Mac G5 you can see that the design of the Athlon 64 doesn't really fit here. And that's always been my point (which thatwendigo seems to want to disagree with).
Interestingly, this article then goes on to discuss the various differences in the methods that Intel, AMD, and IBM (G5) are pursuing to break what they termed the "Frontside Bus Bottleneck." Hint, although there are similarities it's apparent that IBM and AMD are not pursuing the same track.
Here is the link:
http://www.technewsworld.com/story/31594.html
Or how about this (from Geek.com):
"Front Side Bus (FSB) - The speed of the bus connecting the microprocessor, its chipset, and connected main memory. In architectures where the processor interacts directly with main memory, the definition of a singular front side bus is less clear. In such a case you would have to specify two FSB speeds, one for the connection to main memory and one for the connection to the processor chipset."
Which really, I guess, directly supports my position about trying to compare the Athlon 64 "FSB" to the Power Mac G5.
thatwendigo said:
Well, since Arstech specifically asked about the available bus multipliers when they interviewed IBM's Peter Sandon (chief architect on the PPC970) I think that probably indicates that at least some people think that bus multipliers other than 2X are potentially useful. When I went back to this article I found that Peter Sandon said that the "processor design" supports bus multipliers of 2, 3, 4, and 6. However, I think it was unclear whether the PPC970 actually implemented those multipliers (i.e. the design could support them, but it may not be implemented in the 970).
Here is the link where they discuss the bus multipliers:
http://arstechnica.com/cpu/03q2/ppc970-interview/ppc970-interview-2.html
Well, I guess I rest my case (or arguments).
if they are going to bring out the G5 1.8, 2 and 2.2, I wonder how many people will buy them. I (owner of a dual G4) and other friends of mine won't buy any: we will wait for the 2.6 or higher. We have waited to now and we can wait another half a year.
I would be interested in knowing what's your 'strategy'.
I would be interested in knowing what's your 'strategy'.
Yeah, I am pretty stunned that so many of you give Apple absolutely no credit at all. One FULL year passes by with no updates..None. And you think that all apple and IBM can collaborately produce is a measly 200mhz!?!?! Come on people. If it was a dinky 200mhz, it would have been released awwhile ago. Your going to see huge upgrades, and I personally think we have absolutely no clue to teh suprises SJ will unveil.
SyndicateX said:
i think so, too ... if there would be just a 200 mhz upgrade, they would have announced it may 18th or something like that - not @ wwdc - this would be very embarrassing for mister jobs: "well we tried hard, though we couldn't reach the 3ghz - but we came close: 2.2 ghz" ... it looks like this will not happen
just my two cents
.a
fpnc said:
On most architectures, the FSB goes between the CPU and the Northbridge. A private interconnect goes from the Northbridge to the Southbridge. Most I/O ports are on the Southbridge (PCI, ATA, GigE,...).
Since the Opteron has the Northbridge on the chip itself running at the chip clock, this is often referred to as the FSB, even though it differs from traditional architectures (for example, see the table at http://www.amdboard.com/opteron_competition.html).
Another example is at http://www.gamepc.com/labs/view_con...C4A10B57F4FF5B5D8FB815AB7C0EBFE0B95AA08CD40F:
In an Opteron system configuration, the "front side bus" (connector between the CPU and memory) is integrated in the CPU, and runs at the same clock speed as the CPU.
This means the Opteron's FSB speed increases as the clock speed of the Opteron increases as well, and the front side bus of the Opteron 242 chip we're looking at today runs at a whopping 1.6 GHz, twice that of Intel's new 800 MHz front side bus Pentium 4.
7447A watt usage
Motorola's own data sheet on the 7447A shows that at 1.42GHz it typically uses 21 watts and has a maximum usage of 30 watts. So, if the 7447A is theoretically pumped up 1/3 more in frequency to 2GHz, then it should consume a maximum of about 40 watts, which is about 18% less than the maximum you list for the 2GHz 970FX.
When the G4 moves to a 90-nm process in the next few months, then it will probably top out at about 2GHz and have a maximum power use of around 30 watts, which would be about 40% less than the 2GHz 970FX.
The main justifications for making the 970FX was probably for a speed increase and to reduce costs the die size was greatly reduced by leaving the L2 cache the same size as the 970. Could it be that Apple intends to eventually use the 970FX as the lowend 970 in the consumer Macs, in much the same way as Intel reduces the L2 cache for the Celeron line. That way Apple can still justify the price differences in the consumer and pro models and yet still have them both running at the same frequencies. STeve Jobs had stated that Apple intends to be more aggressive on prices with the G5 than they were with the G4. The full scale introduction of the 970FX could be the beginning of those aggressive price reductions.
So, what is the maximum watts do you believe that a 3GHz 970FX will use? I'd venture to guess it will be close to the same as the 2GHz 970.
Apple will have to change the motherboard when the next G4 moves to DDR2. The bus frequency will at least double in speed.
Motorola raised the voltage to enable the G4 to reach 1.42GHz on a 180-nm process. That in turn raised the power use to a typical 35 watts. It seems Apple needed that extra boost in frequency in order to give a better attempt at trying to compete in speed with the Wintel boxes at that time.
Two 7447A processors, both running at 1.42GHz, could use a maximum of 60 watts (30 watts X2 = 60). Which is more than the maximum power use of a 2GHz 970FX. Motorola has already stated that a dual-core G4 (probably made on a 90-nm process) will typically use 25 watts at 1.5GHz.
PC makers have been putting 3GHz desktop Pentium 4 chips in notebook computers for some time now and I don't imagine that there are a lot of noisy high-speed blowers cooling them. Putting a <2GHz 970FX processor in a small form factor desktop box would not be next to impossible judging from that.
thatwendigo said:
Motorola's own data sheet on the 7447A shows that at 1.42GHz it typically uses 21 watts and has a maximum usage of 30 watts. So, if the 7447A is theoretically pumped up 1/3 more in frequency to 2GHz, then it should consume a maximum of about 40 watts, which is about 18% less than the maximum you list for the 2GHz 970FX.
When the G4 moves to a 90-nm process in the next few months, then it will probably top out at about 2GHz and have a maximum power use of around 30 watts, which would be about 40% less than the 2GHz 970FX.
The main justifications for making the 970FX was probably for a speed increase and to reduce costs the die size was greatly reduced by leaving the L2 cache the same size as the 970. Could it be that Apple intends to eventually use the 970FX as the lowend 970 in the consumer Macs, in much the same way as Intel reduces the L2 cache for the Celeron line. That way Apple can still justify the price differences in the consumer and pro models and yet still have them both running at the same frequencies. STeve Jobs had stated that Apple intends to be more aggressive on prices with the G5 than they were with the G4. The full scale introduction of the 970FX could be the beginning of those aggressive price reductions.
So, what is the maximum watts do you believe that a 3GHz 970FX will use? I'd venture to guess it will be close to the same as the 2GHz 970.
Apple will have to change the motherboard when the next G4 moves to DDR2. The bus frequency will at least double in speed.
Motorola raised the voltage to enable the G4 to reach 1.42GHz on a 180-nm process. That in turn raised the power use to a typical 35 watts. It seems Apple needed that extra boost in frequency in order to give a better attempt at trying to compete in speed with the Wintel boxes at that time.
Two 7447A processors, both running at 1.42GHz, could use a maximum of 60 watts (30 watts X2 = 60). Which is more than the maximum power use of a 2GHz 970FX. Motorola has already stated that a dual-core G4 (probably made on a 90-nm process) will typically use 25 watts at 1.5GHz.
Dead God, I hope that you're wrong about the iMac. I like having a computer that doesn't have any fan noise, and they're going to need some high-speed blowers to get rid of the excess. If the formfactor is completely redesigned, then it might be possible we'll see a "G5 iMac" that can double as a hairdryer.
PC makers have been putting 3GHz desktop Pentium 4 chips in notebook computers for some time now and I don't imagine that there are a lot of noisy high-speed blowers cooling them. Putting a <2GHz 970FX processor in a small form factor desktop box would not be next to impossible judging from that.
Okay, thanks for the update. It appears, basically, that you've elaborated on my last post and therefore we now seem to be pretty much in agreement. Frankly, I think the definition provided on Geek.com provides the simplest explanation. In a sense, the Athlon has two Front-side busses. The main memory bus AND the HyperTransport link.
AidenShaw said: