A couple of things to note for the future (some speculation, mind you):
1. The actual dram in the M1 is implemented as separate 8 GB chip(s) on the M1 SoC package (see Apple tech docs); the base MBA/P comes with 8GB as 1 chip, or 16 GB as 2 chips. Obviously, these can be upgraded easily to 32GB or more in future M SoCs, so you get 32GB for the M2 simply by changing out those dram chips on the SoC package;
2. I suspect that the next step will be the M2 for iMac and high end MBP, which will use the Li'fuku *discreet* GPU chip from Apple. This will allow the integrated GPU on the M1 to be removed and the space used to double (+/-) the number of CPU cores for the M2;
3. The M2 will likely use the next bump to the current TSCM 5nm process, yielding more potential chip area, which may be used to increase the CPU cache sizes and perhaps add more neural cores.
One thing I noticed in the event presentation: The M1 has a 12MB *L2* cache! On Intel processors they have been using a 3-level memory cache architecture for years. On Intel, it would be the L3 cache that would be that large, not the L2 cache, which would normally be down in the 128kB - 256kB range. Apple removing a cache level (3 -> 2) is a big deal, because it reduces memory latency and saves space/power.
Just my take on it.