Since then, TSMC confirmed in conference call comments that its chip packaging changes have led to improvements of 20 percent in both speed and packaging thickness and 10 percent in thermal performance. This has a number of implications for future device performance and future foundry partner selection for Apple.
First, it is helpful to understand why InFO-WLP (Integrated Fan-Out Wafer-Level Packing) is such an important development for Apple's mobile processors. Typically, chips as large as CPUs or mobile SoCs have been attached via "flip-chip" methods which attach an array of inputs and outputs to a package substrate via solder bumps, ultimately enabling it to be attached to a printed circuit board (PCB) for device integration.
From the start, this is a compromise, as it would be preferable to attach a silicon die directly to the PCB to minimize height and reduce the lengths of interconnects between components. A number of technical limits in areas such as interconnect pitch, board produceability, and damage due to board warpage typically prevent this direct attachment.
The above problem had previously been circumvented for smaller I/O count components with a similar concept called Fan-In Wafer-Level Packing, where smaller dies are allowed to route their inputs and outputs in an area roughly the same area as the die. TSMC is just one of many companies beginning to enable this concept for larger I/O count devices in such a way that allows high volume, acceptable yields, and an acceptable cost.
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Article Link: How TSMC Won Back Exclusivity With Apple for the A10 Chip in iPhone 7
