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Originally posted by Hemingray
As to how this all calculates out, does anyone know if the current G5's are even close to max-ing out the current Hypertransport bandwidth? I'm also assuming that, like with FireWire or USB, Hypertransport 1.x can't be upgraded to 2.0.
We can try to do a little back-of-the-napkin math on this. I'll do as much of this as I can off the top of my head. :)

The G5 has two HyperTransport links: a 16-bit one (3.2 GBps max) between U3 and the PCI bridge, and an 8-bit one (1.6 GBps max) between the PCI bridge and K2. The latter is connected to the following, with peak MBps numbers in bold (feel free to challenge/clarify me on the numbers, everybody :) ):

FireWire 100
USB 2.0 ~70 (not a typo; figure one port at 60 MBps and four others at 1.5 MBps each)
Ethernet 125
SATA 2 x 150
Digital audio: 6 channels x 2 ports x 48,000 samples/sec x 24 bits per sample = 1.6 (this is not significant, but I want to cover all the bases)
AirPort Extreme 6.75
ATA/100 100

OK, I don't think I forgot anything. 100 + 70 + 125 + 300 + 10 (rounding) + 100 = 705 MBps. That's about half of the theoretical max.

I chickened out just now and checked the website, and that appears to be correct. I did leave out the boot ROM and the PMU, because I figure their bandwidth is truly insignificant. But I'm not sure about a couple things: my impression is that there's only one FireWire bus for all three ports. Does anyone know if this is correct? Does it really mean that the maximum total bandwidth for FireWire is 800 Mbps = 100 MBps, or is there another 400 Mbps = 50 MBps for the FireWire 400 ports?

Now for the 16-bit link. On the 1.8 and 2.0 GHz configurations, there are three PCI-X slots on two buses. Let's suppose that each bus can run at 133 MHz (which is not supported by the block diagram, but what the heck). 133 MHz x 64 bits x 2 buses = 2.08 GBps. Add this to our 705 MBps number from before and we get 2.767 GBps, which is about 400-some MBps short of the max.

Now, we also have to consider that almost all the I/O bandwidth numbers I've mentioned have been for interfaces that can (theoretically) do them entirely in one direction. But 16-bit HyperTransport is only capable of 3.2 GBps in both directions simultaneously. It can only do 1.6 GBps in each direction. So that may be a design consideration. On the other hand, I have to figure it's pretty rare that every single interface on your system will be sending data to the processor at once (as opposed to being sent data), so HyperTransport would have a big advantage over a unidirectional bus like PCI (?) that would (I think) have a lot of overhead due to switching directions all the time.

It's also somewhat important to note that the number we're actually looking at is not 1.6 GBps, but 1.5625 GBps (someone divided by 1000 instead of 1024), and there's also some overhead due to the address multiplexing and other things that I don't understand much about.

FWIW
WM

For your edification:
03107301P1724_01.gif


That's from the developer note.
 
Wow...its always refreshing to see someone on the site that knows what they are talking about....great explenation of everything!
 
Originally posted by RBMaraman
Wait...You thought I was talking about Hypertransport...LOL! Oh my Gosh! I so totally was talking about another technology! LOL! Oh my Gosh! I can't believe you fell for it!

<Silence>

<Silence>

<Crickets Chirp>

Yeah, I'm just trying to keep myself from sounding like a complete idiot. I guess I should really learn to read the articles before I start posting.

I'm so freaking sad.... I thought you were talking about "HYPERDRIVE" technology!!!
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Pass me the hydrospanner!

"No this one goes there, that one goes there!"-
H.Solo (on hoth)
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-
 
Originally posted by WM.
We can try to do a little back-of-the-napkin math on this. I'll do as much of this as I can off the top of my head. :)

The G5 has two HyperTransport links: a 16-bit one (3.2 GBps max) between U3 and the PCI bridge, and an 8-bit one (1.6 GBps max) between the PCI bridge and K2. The latter is connected to the following, with peak MBps numbers in bold (feel free to challenge/clarify me on the numbers, everybody :) ):

FireWire 100
USB 2.0 ~70 (not a typo; figure one port at 60 MBps and four others at 1.5 MBps each)
Ethernet 125
SATA 2 x 150
Digital audio: 6 channels x 2 ports x 48,000 samples/sec x 24 bits per sample = 1.6 (this is not significant, but I want to cover all the bases)
AirPort Extreme 6.75
ATA/100 100

OK, I don't think I forgot anything. 100 + 70 + 125 + 300 + 10 (rounding) + 100 = 705 MBps. That's about half of the theoretical max.

I chickened out just now and checked the website, and that appears to be correct. I did leave out the boot ROM and the PMU, because I figure their bandwidth is truly insignificant. But I'm not sure about a couple things: my impression is that there's only one FireWire bus for all three ports. Does anyone know if this is correct? Does it really mean that the maximum total bandwidth for FireWire is 800 Mbps = 100 MBps, or is there another 400 Mbps = 50 MBps for the FireWire 400 ports?

Now for the 16-bit link. On the 1.8 and 2.0 GHz configurations, there are three PCI-X slots on two buses. Let's suppose that each bus can run at 133 MHz (which is not supported by the block diagram, but what the heck). 133 MHz x 64 bits x 2 buses = 2.08 GBps. Add this to our 705 MBps number from before and we get 2.767 GBps, which is about 400-some MBps short of the max.

Now, we also have to consider that almost all the I/O bandwidth numbers I've mentioned have been for interfaces that can (theoretically) do them entirely in one direction. But 16-bit HyperTransport is only capable of 3.2 GBps in both directions simultaneously. It can only do 1.6 GBps in each direction. So that may be a design consideration. On the other hand, I have to figure it's pretty rare that every single interface on your system will be sending data to the processor at once (as opposed to being sent data), so HyperTransport would have a big advantage over a unidirectional bus like PCI (?) that would (I think) have a lot of overhead due to switching directions all the time.

It's also somewhat important to note that the number we're actually looking at is not 1.6 GBps, but 1.5625 GBps (someone divided by 1000 instead of 1024), and there's also some overhead due to the address multiplexing and other things that I don't understand much about.

FWIW
WM

For your edification:
03107301P1724_01.gif


That's from the developer note.

Where are they going to fit the "Warp Core"???
 
Originally posted by spencecb
Wow...its always refreshing to see someone on the site that knows what they are talking about....great explenation of everything!
I wouldn't say I'm there yet. :) I'd hope that that block diagram is pretty self-explanatory. See how the HyperTransport links and the buses to the processors are the only ones on the diagram represented by two arrows, instead of a solid line? That tells you about bidirectional vs. unidirectional connections (although I wouldn't rely on a detail in a diagram like that to know for sure). The only praise I might allow you to give me ;) would be for doing most of that off the top of my head (I went to the developer site only at the last minute, to confirm everything and attach the image).

It's amazing what you can learn on developer.apple.com, even if you're not a member of the ADC!! :) Check it out!

WM
(not a member of the ADC, although I may be eventually)

Oh, again, if anyone has any corrections/clarifications/challenges on my numbers there, feel free...
 
Originally posted by iriejedi
Where are they going to fit the "Warp Core"???
They do have exotic names, huh? "HyperTransport" is sure a long ways from "60x" or even "MaxBus"...that's marketing innovation (ha!) for you.

WM
 
Originally posted by pilotgi
We won't be seeing any computers with this new technology for a while. It's going to do away with the agp slot.

Know anywhere you can get a graphics card that doesn't use agp or pci?

Wouldn't this help the card vendors from the Siggraph thread (page 1) and be perfect for the on-board quad-980 workstation?

Hypertransport is the inter chip connect bus.

Rocketman
 
Originally posted by VectorWarrior
If this is related to new powermacs then surely they would be available immediatly. If there is to be an announcement and then a waiting period why announce this now and not later when the units actually ship.

Because this is not an announcement by Apple.
 
Originally posted by Mav451
I don't see why they would put this into the existing G5 system because that would lead to an entirely new motherboard...pretty much tossing ou the Rev B argument. New technology usually leads to a new product, not a simple revision...


It is a bit more complicated than that as well. The Opteron and the G5 uses the HyperTransport differently in their system architectures. On the G5 it is essentially used as a superfast I/O bus, but otherwise the architecture of the G5 is vanilla SMP and doesn't fully exploit the theoretical capabilities of the HyperTransport technology. There is not a pressing need to upgrade the HyperTransport version primarily because Apple isn't fully exploiting the one they have. Therefore, it would be cheaper for Apple to stick with their current version for at least another year.

The Opteron actually uses the HT as a ccNUMA fabric, not a simple SMP I/O controller. Since HT is basically an AMD owned technology, they exploited it to great effect in their multiprocessor Opteron systems and generally get more out of it. The v2.0 will allow the Opterons to scale well to even larger multi-processor systems than it already does (currently 8-way for Opteron versus 2-way for SMP systems), but I don't see any pressing need on the G5 for even more I/O throughput as there are other rate limiting factors.
 
You may see HT2.0 coming quicker than USB2.0 -- about the time DDR2 and PCI-Express show up.

AMD may have made the announcement about supporting a PCI-Express HT Tunnel under HT2.0 -- but as you can see this is mainly helpful for PCI and the bridge to KeyLargo2 and the i/o there (which is basically lashed together with PCI/USB).

HT2.0 won't make the memory, graphics card, or FSB any faster.

Just a bigger bandwidth pipe from the UniNorth 3.x to the PCI bus and i/o.
 
Originally posted by RBMaraman
Wait...You thought I was talking about Hypertransport...LOL! Oh my Gosh! I so totally was talking about another technology! LOL! Oh my Gosh! I can't believe you fell for it!

<Silence>

<Silence>

<Crickets Chirp>

Yeah, I'm just trying to keep myself from sounding like a complete idiot. I guess I should really learn to read the articles before I start posting.

LOL! A very good recovery
 
not to mention you guys forgot to include the RAM bandwidth...

even with that, though, 2 processors aren't using HT1.0 fully, anyway...
 
Originally posted by benpatient
not to mention you guys forgot to include the RAM bandwidth...

even with that, though, 2 processors aren't using HT1.0 fully, anyway...

Since the ram doesn't go over HT, no, they didn't forget.

The main thing that's cool about this is that it bridges to PCI-Express easily, which should keep Apple from getting left behind by Intel and Co. when they switch away from AGP. Maybe let them simplify that block diagram a bit too.
 
Apple Connection ?

Isn't Apple connected some kind of way with some "hypertransport" consortium ? or something like that ?

Just wondering if that is the case, might they not have been aware of this change coming for awhile ? and if so, maybe it is possible to see it hopefully sooner than later in future G5 releases ?

Still holding on to my G4/450.. one of these days gonna get that new Mac.. and they just keep gettin' faster and faster :)
 
Originally posted by Sun Baked
...KeyLargo2 and the i/o there (which is basically lashed together with PCI/USB).
Eh? Certainly the external USB ports and the AirPort card are on a PCI bus, but I wouldn't say the SATA, FireWire, or Ethernet ports on K2 have much to do with USB or PCI.

On the other hand, there certainly could be something you know that I don't. As I said, I'm not a member of the ADC, and my understanding is that there were sessions at WWDC about the G5's architecture, which I certainly don't have access to. And I suppose anyone who does is probably under NDA...
HT2.0 won't make the memory, graphics card, or FSB any faster.

Just a bigger bandwidth pipe from the UniNorth 3.x to the PCI bus and i/o.
Agreed.

WM
 
Unafraid

Just reading while listening to Swordfish soundtrack and was wondering.

VT's Supercomputer needed low-latency interconnects and opted to use Infineon fibre connection and not the SPDF that Apple offers; why?? Bandwidth for computational power??

Now apply this new HyperTransport ver2.0 for this in Dual or Quad G5's in a Rack mount....say XServe Supreme and link to XRaids.

Or better yet implement DDR-II memory with said above and allow HyperTransport as an effective data bus Throughout the mobo......to everything.

Say 12x SuperDrives, all 3 nah say 4 FULL PCI-X 133Mhz 64-bit slots or maybe PCI-Extreme. Now what about PowerMac G5s or Xserves able to use memory with supremely low latency across an entire network (local, but imagine over 3x the speed of T1 internet connection networks). Your G5 doing gene splicing, applying nanotechnology in a hypothetical realm to build synthetic materials or even bones, ligaments, tendons, that are built from existing molecules in nature yet modified to 100x tensile strength of Titanium......but to research this from scratch all the systems need low latency from memory to cpu's to HDD to input output (including Infineon Fibre connection and local 10000Base T Ethernet etc).

Well you get my drift, the Enterprise computer with a sweet voice, sweet mind, and can go 0-naked in a heartbeat.

LOL:D

Seriously we might have to wait to see what AMD can do with this first before hoping for it in Apple products ....only because they've used it first thus may have more expertise.
 
According to NeatGekko

According to NeatGekko we could see new powermacs at anytime in February and definitely in February. He suggests any Tuesday as a possible release date and is hoping for tomorrow. He did not comment on the powermacs using this new technology, however.
 
Re: Apple Connection ?

Originally posted by kansast
Isn't Apple connected some kind of way with some "hypertransport" consortium ? or something like that ?

Just wondering if that is the case, might they not have been aware of this change coming for awhile ? and if so, maybe it is possible to see it hopefully sooner than later in future G5 releases ?

Yes, Apple is a member of the HyperTransport Consortium.
 
Re: Unafraid

Originally posted by Prom1
VT's Supercomputer needed low-latency interconnects and opted to use Infineon fibre connection and not the SPDF that Apple offers; why?? Bandwidth for computational power??

S/PDIF is an audio connect - toslink :). They won't be getting very much bandwidth off of that!

However, they do use the built in gigabit ethernet as a backup, but ethernet isn't as low latency.
 
G5s do not use HyperTransport to talk between CPUs to main memory. HyperTransport is only used to talk between the north bridge to the south bridge (8 bit at 400MHz), and between north bridge and PCI bridge (16 bit at 800MHz).

WM, you cannot add the PCI budget to the rest of the I/O budget. Since the busses are separate, the budgets are separate. So, in effect, there is ample headroom on both busses (approx 705 and 800[x2], on the 8 bit at 400MHz), (2.08 and 1.6[x2], on the 16 bit at 800MHz).

What is going on here is in AMD's best interest since they use HyperTransport as their processor interconnect. They need to get that up to higher transfer rates or else their fast processors will go hungry for data. Current Opterons use three 16 bit at 1600MHz HyperTransport busses, thats 9.6GBps each way!
 
Re: Unafraid

Originally posted by Prom1
Well you get my drift, the Enterprise computer with a sweet voice, sweet mind, and can go 0-naked in a heartbeat.

LOL:D

First dibs on the Holodeck!!! :D
 
Originally posted by Frohickey
WM, you cannot add the PCI budget to the rest of the I/O budget. Since the busses are separate, the budgets are separate. So, in effect, there is ample headroom on both busses (approx 705 and 800[x2], on the 8 bit at 400MHz), (2.08 and 1.6[x2], on the 16 bit at 800MHz).

Actually, his original analysis was right. The south bridge has to go through the PCI bridge to get to the north bridge, which means that there is 3.2 GBps bandwidth to everything but RAM & AGP, and 1.6 GBps max beyond PCI-X.
 
Re: Re: Unafraid

Originally posted by Rincewind42
S/PDIF is an audio connect - toslink :). They won't be getting very much bandwidth off of that!

However, they do use the built in gigabit ethernet as a backup, but ethernet isn't as low latency.
I think it was a joke...notice the Swordfish reference. I've only seen a bit of that movie, but I have the impression that there's a lot of meaningless technobabble tossed about. :)

Admittedly, my techno-nerd shields were up too and I was ready to come out with debunking guns blazing, but then I re-read it...

:cool:

WM
 
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