IBM Opens Cell Processor

[alandail]

OS X is based on BSD UNIX, not Linux. And there is a vast difference between getting Linux (or even Darwin) running on a chip and getting the entire OS X experience ported (heck, Darwin can run on x86 chips, but that doesn't mean that OS X does).

The cell is a PPC + other processors on a single chip - the PPC is the controller and should be able to run OS X unmodified. There is really no reason to think otherwise. In fact, there is every reason to think that the PPC that is inside the cell is the same PPC that MS is using in the new XBox. While the OS clearly could benefit from taking advantage of the other processors in the cell, those changes wouldn't have to be done to get the OS up and running.

And for the record, there is every reason to think the full OS X (minus classic) runs on x86 hardware in apple's labs. It would be a mistake for Apple to not maintain compatible builds of each major release.

 

[Chryx]

Well I made this comment before, but I'll make it again. We know that the PPE unit is based on the POWER architecture. This however does not mean that it can actually run PPC code. For example. The Athlon 64 is based on x86, BUT if they had not added extra instructions, the Athlon 64 could not run x86-32 bit. It all comes donw to the art of logic reasoning.

What is also interesting is the folowing: The Playstation 3 emulates PS1 and PS2 for backwards compatibility Both the PS1 and PS2 are PPC computers. Of course it is not exactly clear what is being emulated. Maybe the code itself can run unemulated and just the hardware is emulated. Of notice is that also the PS2 emulates the PS1.
Naturally.

Firstly, the Athlon64 is an EXTENDED AthlonXP (wider registers, SSE2 support in microcode through the existing execution hardware, ondie memory controller, hypertransport for I/O), it doesn't HAVE '32bit added instructions', it's a 32bit core that's been 'stretched' for 64bit usage.

secondly, the Playstation 2 is MIPS based, not PowerPC, and PS2 uses the entirety of a PS1 as it's I/O controller, hence the backwards compatability.


using Logic and reasoning is all well and good, but you might want to check your reasoning using correct variables before implying everyone else is wrong.

 

[isgoed]

Firstly, the Athlon64 is an EXTENDED AthlonXP (wider registers, SSE2 support in microcode through the existing execution hardware, ondie memory controller, hypertransport for I/O), it doesn't HAVE '32bit added instructions', it's a 32bit core that's been 'stretched' for 64bit usage.

Please!! Even without having read this I could deduce this. If you have only 64 bit adresses an array of 32 bit Ptr's does not work. Take a look at: http://arstechnica.com/cpu/03q1/x86-64/x86-64-4.html You can see that the Athlon 64 even has a whole logic-area full of transistors to support Legacy Mode. It all comes down to logic and a good memory (march 2003)

secondly, the Playstation 2 is MIPS based, not PowerPC, and PS2 uses the entirety of a PS1 as it's I/O controller, hence the backwards compatability.

OK, the PS(1/2) is MIPS. I got confused with RISC, which they both are.

using Logic and reasoning is all well and good, but you might want to check your reasoning using correct variables before implying everyone else is wrong.

Well I only used examples to outline my reasoning. My original conclusion is not affected by the validy of my arguments (since it were examples only). My conclusion still holds.

 

[Chryx]

Please!! Even without having read this I could deduce this. If you have only 64 bit adresses an array of 32 bit Ptr's does not work. Take a look at: http://arstechnica.com/cpu/03q1/x86-64/x86-64-4.html You can see that the Athlon 64 even has a whole logic-area full of transistors to support Legacy Mode. It all comes down to logic and a good memory (march 2003)

You've got it the wrong way around still, K8 is a K7 with 64bit extensions strapped on, it doesn't have 'extra logic' for 32bit mode, it has extra transistors for 64bit mode, it wasn't designed from the ground up, it was adapted from an existing architecture.

It's still an irrelevant example anyway, because PowerPC has ALWAYS been a 64bit arch, even if the consumer implementations of it haven't been, whereas the entire architecture gets an overhaul in the move from 32bit x86 to 64bit x86, the only notable difference between 32bit implementations of PPC and 64bit is the native integer word length and memory address space.

OK, the PS(1/2) is MIPS. I got confused with RISC, which they both are.

RISC/CISC is a fairly meaningless seperator these days really, almost all modern micro-architectures break instructions down into micro-ops

Well I only used examples to outline my reasoning. My original conclusion is not affected by the validy of my arguments (since it were examples only). My conclusion still holds.

That simply doesn't hold, if the baseline material is wrong, no conclusions brought about from that can be accurate.


That, and a PowerPC + VMX cpu that can't actually run PowerPC or VMX code... ISN'T a PowerPC + VMX cpu.. inherently, if it is incompatible with those instruction sets, then it isn't a CPU implementing that ISA.

QED

 

[aussie_geek]

Have a read...

I don't think the Cell is quite so limited. I've read through this fantastic explanation:

http://www.blachford.info/computer/Cells/Cell1.html

It's the future of CPUs, Apple would be foolish not to work with IBM to modify it to make the fastest freakin' Mac ever (or PC for that matter.)

Screw the talks with Intel, they've already got an "in" to the next best thing.

Joe

Excellent read!! Looks like there are great things coming around the corner.

aussie_geek

 

[isgoed]

So wrong

You've got it the wrong way around still, K8 is a K7 with 64bit extensions strapped on, it doesn't have 'extra logic' for 32bit mode, it has extra transistors for 64bit mode, it wasn't designed from the ground up, it was adapted from an existing architecture.

I have provided a hard evidence link, by deduced reasoning emphasised this evidence and still you don't get it? I even wanted to point out to you the K7 and K8 cores, but since you do it yourself I am absolutely baffled that you keep persisting that the K8 is a derivative of the K7. THE K8 IS A FREAKING NEW DESIGN! You better admit I am right. That would be less an embaressment than how you portrait yourself now. I at least know when I am wrong (The playstation example).

It's still an irrelevant example anyway, because PowerPC has ALWAYS been a 64bit arch, even if the consumer implementations of it haven't been, whereas the entire architecture gets an overhaul in the move from 32bit x86 to 64bit x86, the only notable difference between 32bit implementations of PPC and 64bit is the native integer word length and memory address space.

LOGIC: the purpose of an example is not its relevance but its analogy.

That simply doesn't hold, if the baseline material is wrong, no conclusions brought about from that can be accurate.

Of which your own sentence is a wonderfull example. You incorrectly identify my baseline material, so your conclusion is wrong. My baseline material is not the EXAMPLE of 64bit-x86 (which is even correct), but my baseline material lies at the heart of logic and is:

If an entity is a derivative of another entity does not mean that those entities provide the same behaviour.

Or in this context:

That Cell is based on PPC architecture does not mean that it can run PPC code.

That, and a PowerPC + VMX cpu that can't actually run PowerPC or VMX code... ISN'T a PowerPC + VMX cpu.. inherently, if it is incompatible with those instruction sets, then it isn't a CPU implementing that ISA.

This is what I am trying to say all along. So I take the credits for this. Thank you very much.

QED

What have you exactly demonstrated? It sure aint your right.

 

[Chryx]

I have provided a hard evidence link, by deduced reasoning emphasised this evidence and still you don't get it? I even wanted to point out to you the K7 and K8 cores, but since you do it yourself I am absolutely baffled that you keep persisting that the K8 is a derivative of the K7. THE K8 IS A FREAKING NEW DESIGN! You better admit I am right. That would be less an embaressment than how you portrait yourself now. I at least know when I am wrong (The playstation example).

Except you're wrong now, the K8 design is based off of the K7 design, heavily modified, sure, but not an entirely new design.

To use another example:

PowerPC 750 = 2+branch issue <
PowerPC 7400 = 2+branch issue, lower latency FPU, Altivec <
PowerPC 7450 = 3+branch issue, much longer longer pipelines

K7 = 32bit, 3 issue, 128KB L1 cache, 9 execution units (3/3/3 decoder/integer/FP split)

K8 = 32/64bit, 3 issue, 128KB L1 cache, 9 execution units (3/3/3 decoder/integer/fp split) - slightly longer pipeline

If you run CPU bound (fits in cache) 32bit code on a K8 and a K7, clock normalised they'll typically perform IDENTICALLY.

I'm not about to admit you're right, simply because, well, you aren't. K8 is a heavily modified K7 design, not a design from the ground up.

 

[isgoed]

Except you're wrong now, the K8 design is based off of the K7 design, heavily modified, sure, but not an entirely new design.

To use another example:

PowerPC 750 = 2+branch issue <
PowerPC 7400 = 2+branch issue, lower latency FPU, Altivec <
PowerPC 7450 = 3+branch issue, much longer longer pipelines

K7 = 32bit, 3 issue, 128KB L1 cache, 9 execution units (3/3/3 decoder/integer/FP split)

K8 = 32/64bit, 3 issue, 128KB L1 cache, 9 execution units (3/3/3 decoder/integer/fp split) - slightly longer pipeline

If you run CPU bound (fits in cache) 32bit code on a K8 and a K7, clock normalised they'll typically perform IDENTICALLY.

I'm not about to admit you're right, simply because, well, you aren't. K8 is a heavily modified K7 design, not a design from the ground up.

Keep your pride, I don't care.

 

[Chryx]

Keep your pride, I don't care.

I'll take that as acknowledgement that you know you've been shooting your mouth off from a position of ignorance.

p.s. IBM have Cell related stuff under the Power architecture section on their website, since PowerPC/AS is the actual ISA in modern POWER chips.. that pretty much seals the deal, you've been wrong for the entire thread. good day.

 

[blitzkrieg79]

Make love not war please... Anyway that reminds me, has anyone heard any rumors on the development of IBM Power 6? I wonder how much the Power 6 will borrow from the CELL design... I mean if CELL really is what it is cracked up to be then why would IBM develop a nonCell or nonCell related processor, I know Power series are supposed to be server processors but then why is IBM pushing this CELL everywhere thing and opening up the CELL architecture to suit individual needs...

I guess there is nothing worng with having two totally different processor lines but then again IBM recently had in plans to lay off a couple of thousands of people because they had to "restructure" so I guess they are looking everywhere to save as much money as possible and to borrow the CELLlike architecture in developing the Power6 certainly would seem to save them some money. Also I have read somewhere that Power6 is supposed to sport "large frequency enhancements" and CELL (or CELL derived design) definately suits that...

 

[bokdol]

wow that was the most amazing viewing of geek war, i have ever seen. will not really, but it was a fun little banter.

 

[Chryx]

wow that was the most amazing viewing of geek war, i have ever seen. will not really, but it was a fun little banter.

Learn to use the geek side of the force, and you will achieve a power greater than any wannabe.