fklehman said:
P.S.: do we know yet what kind of G5 is in there? the 3x bus multiplier is odd. Is that jut Apple hobbling the iMac for product differentiation, or might there be a different proc in there? There's been specualtion elsewhere that it's the low-power G5 overclocked to 1.9/2.1 because heat has been an issue in the previous iMacs and even overclocked the 970GX (that's the low-power one right?) gives off less heat. Just a thought.
First, the G5 itself supports all kind of multipliers, like 2, 2.5, 3 and probably a few more so there is nothing weird about a 3x multiplier per se. Now why did they choose this multiplier? There are two important things with memory access: Bandwidth and latency. Latency is on the order of 100 nS. At 2 GHz, that is about 200 processor cycles. Whether the bus runs at 2x or 3x doesn't make the slightest differences (the only difference is that you wait 100 bus cycles at 2x or 67 bus cycles at 3x, but the time is the same).
The other thing is bandwidth. Here the multiplier has some importance: A G5 can both read and write four bytes every eight out of nine bus cycles (in other words, it can both read and write 32 bytes every nine bus cycles). At 2.1 GHz and 2x multiplier, 1050 MHz bus, that would be 3733 MByte per second, both read and write. At 3x multiplier, 700 MHz bus, that would be 2489 MByte per second, both read and write.
If you do reads and writes simultaneously, you would need RAM chips capable of handling 7466 MByte per second, or the 1050 MHz bus is wasted. Even at 700 MHz, the RAM chips won't be able to handle the 4978 MByte/second maximum. If you only read or only write, then there is a good chance that the processor won't need more than 2489 MByte/sec anyway. So 700 MHz bus speed is unlikely to slow you down, and it will save a lot of money (building a 1050 MHz part connecting to RAM is much much harder than building a 700 MHz part); it will use less power and make the machine much easier to build.
For the towers, it is a bit different: There are two processors, so they can produce twice as many reads/writes per cycle than a single processor, and they both go through the same bus. The RAM is also doubled and can provide twice as much bandwidth. In this configuration, the 700 MHz bus would be the bottleneck. In a tower, two of the three parties involved (CPU and RAM) can handle twice as much bandwidth, so you want the bus speed improved as well.
I would be curious to run some serious memory benchmarks on a quad processor system: I am sure there the memory must be the limiting factor (there are four CPUs instead of two, two buses instead of one, but the same memory).
